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drm/amd/display: add per pipe dppclk

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v2: Fix commit title

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dmytro Laktyushkin
2018-02-12 15:19:20 -05:00
committed by Alex Deucher
parent 8ff15a8fcc
commit f553e68102
5 changed files with 28 additions and 17 deletions
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2
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
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@@ -996,7 +996,7 @@ bool dcn_validate_bandwidth(
dc->debug.min_disp_clk_khz;
}
context->bw.dcn.calc_clk.dppclk_div = (int)(v->dispclk_dppclk_ratio) == 2;
context->bw.dcn.calc_clk.max_dppclk_khz = (int)(v->dppclk * 1000);
for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];