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drm/amdgpu: fix missing stuff in NBIO v7.11

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add get_clockgating_state, update_medium_grain_light_sleep and
update_medium_grain_clock_gating in nbio_v7_11_funcs
v1:
add missing funcs in nbio_v7_11.c
v2:
modify the if condition and add spport for nbio v7.11 clockgating.

Signed-off-by: Li Ma <li.ma@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Li Ma
2023-10-16 14:36:26 +08:00
committed by Alex Deucher
parent 66d64e4e03
commit fa9dd7a285
4 changed files with 97 additions and 1 deletions
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6
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h
View File

@@ -775,6 +775,12 @@
#define regPCIE_USB4_ERR_CNTL5_BASE_IDX 5
#define regPCIE_USB4_LC_CNTL1 0x420179
#define regPCIE_USB4_LC_CNTL1_BASE_IDX 5
#define regBIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL 0x420118
#define regBIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL_BASE_IDX 5
#define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2 0x42001c
#define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2_BASE_IDX 5
#define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1 0x420187
#define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1_BASE_IDX 5
// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp

13
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h
View File

@@ -24634,7 +24634,18 @@
//PCIE_USB4_LC_CNTL1
#define PCIE_USB4_LC_CNTL1__PCIE_USB_ROUTER_CLEAR_PATH_MODE__SHIFT 0x0
#define PCIE_USB4_LC_CNTL1__PCIE_USB_ROUTER_CLEAR_PATH_MODE_MASK 0x00000001L
//BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL
#define BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x00000001L
#define BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x00000002L
#define BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK 0x00000020L
#define BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK 0x00000040L
#define BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK 0x00000080L
#define BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x00000100L
//BIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x00010000L
//BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK 0x00000001L
#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK 0x00000008L
// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp
//BIF_CFG_DEV0_RC0_VENDOR_ID