2 Commits

Author	SHA1	Message	Date
Rohit Agarwal	2cabc45237	dt-bindings: clock: Add A7 PLL binding for SDX65 ... Add information for Cortex A7 PLL clock in Qualcomm platform SDX65. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1645505785-2271-2-git-send-email-quic_rohiagar@quicinc.com	2022-03-08 16:17:40 -06:00
Manivannan Sadhasivam	ee778e069d	dt-bindings: clock: Add Qualcomm A7 PLL binding ... Add devicetree YAML binding for Cortex A7 PLL clock in Qualcomm platforms like SDX55. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210118041156.50016-4-manivannan.sadhasivam@linaro.org Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2021-02-08 09:46:23 -08:00