Konrad Dybcio
23eeae60b0
drm/msm/a6xx: Add missing regs for A7XX
...
Add some missing definitions required for A7 support.
This may be substituted with a mesa header sync.
Tested-by: Neil Armstrong <neil.armstrong@linaro.org > # on SM8550-QRD
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org > # sm8450
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/559282/
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-10-09 11:22:05 -07:00
Konrad Dybcio
b3ba797e45
drm/msm/a6xx: Add some missing header definitions
...
Add a definition of the GMU_AHB_FENCE_STATUS_CLR reg and CP_PROTECT_CNTL
bitfields.
This may be substituted with a mesa header sync.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/543330/
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-08-07 14:30:49 -07:00
Rob Clark
f73343fae5
drm/msm: Update generated headers
...
It's been a bit overdue. Regen headers to pull in a2xx perfcntr
updates, etc.
Signed-off-by: Rob Clark <robdclark@chromium.org >
Patchwork: https://patchwork.freedesktop.org/patch/527926/
Link: https://lore.kernel.org/r/20230320185416.938842-2-robdclark@gmail.com
2023-03-21 09:10:47 -07:00
Akhil P Oommen
1e05bba5e2
drm/msm/a6xx: Update a6xx gpu coredump
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Update gpu coredump for a660/a650 family of gpus with the extra
information available.
Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com >
Patchwork: https://patchwork.freedesktop.org/patch/515608/
Link: https://lore.kernel.org/r/20221221203925.v2.3.Ifbfce6d693b202dac92006345bb825e7c5aee9c6@changeid
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-01-16 10:35:51 -08:00
Akhil P Oommen
3a9dd708b9
drm/msm/a6xx: Improve gpu recovery sequence
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We can do a few more things to improve our chance at a successful gpu
recovery, especially during a hangcheck timeout:
1. Halt CP and GMU core
2. Do RBBM GBIF HALT sequence
3. Do a soft reset of GPU core
Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com >
Patchwork: https://patchwork.freedesktop.org/patch/498400/
Link: https://lore.kernel.org/r/20220819015030.v5.6.Idf2ba51078e87ae7ceb75cc77a5bd4ff2bd31eab@changeid
Signed-off-by: Rob Clark <robdclark@chromium.org >
2022-08-28 09:29:27 -07:00
Rob Clark
57cfe41c5f
drm/msm: Update generated headers
...
Update headers from mesa commit:
commit 7e63fa2bb13cf14b765ad06d046789ee1879b5ef
Author: Rob Clark <robclark@freedesktop.org >
AuthorDate: Wed Mar 2 17:11:10 2022 -0800
freedreno/registers: Add a couple regs we need for kernel
Signed-off-by: Rob Clark <robdclark@chromium.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15221 >
Signed-off-by: Rob Clark <robdclark@chromium.org >
[for display bits:]
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com >
Link: https://lore.kernel.org/r/20220304005317.776110-2-robdclark@gmail.com
2022-03-04 11:50:41 -08:00
Rob Clark
cc4c26d4ae
drm/msm: Generated register update
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Based on mesa commit daa2ccff7a0201941db3901780d179e2634057d5
Small bit of .c churn in the phy code to adapt to split up of phy
related registers.
Signed-off-by: Rob Clark <robdclark@chromium.org >
2021-06-23 07:33:54 -07:00
Rob Clark
c28c82e9db
drm/msm: sync generated headers
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We haven't sync'd for a while.. pull in updates to get definitions for
some fields in pkt7 payloads.
Signed-off-by: Rob Clark <robdclark@chromium.org >
Acked-by: Jordan Crouse <jcrouse@codeaurora.org >
Signed-off-by: Rob Clark <robdclark@chromium.org >
2020-07-31 06:46:16 -07:00
Jonathan Marek
24e6938ec6
drm/msm/a6xx: update a6xx_hw_init for A640 and A650
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Adreno 640 and 650 GPUs need some registers set differently.
Signed-off-by: Jonathan Marek <jonathan@marek.ca >
Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org >
Signed-off-by: Rob Clark <robdclark@chromium.org >
2020-05-18 09:26:33 -07:00
Sharat Masetty
e812744c5f
drm: msm: a6xx: Add support for A618
...
This patch adds support for enabling Graphics Bus Interface(GBIF)
used in multiple A6xx series chipets. Also makes changes to the
PDC/RSC sequencing specifically required for A618. This is needed
for proper interfacing with RPMH.
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org >
Signed-off-by: Rob Clark <robdclark@chromium.org >
2020-01-02 16:05:36 -08:00
Rob Clark
ccdf7e28b4
drm/msm: update generated headers
...
Signed-off-by: Rob Clark <robdclark@gmail.com >
2018-12-11 13:05:27 -05:00
Rob Clark
a69c5ed25d
drm/msm: update generated headers
...
Signed-off-by: Rob Clark <robdclark@gmail.com >
2018-10-07 14:40:19 -04:00
Jordan Crouse
f8fc924e08
drm/msm/a6xx: Fix PDC register overlap
...
The current design greedily takes a big chunk of the PDC
register space instead of just the GPU specific sections
which conflicts with other drivers and generally makes
a mess of things.
Furthermore we only need to map the GPU PDC sections
just once during init so map the memory inside the function
that uses it and adjust the pointers and register offsets
accordingly.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org >
Signed-off-by: Rob Clark <robdclark@gmail.com >
2018-10-03 20:24:54 -04:00
Rob Clark
2d75632253
drm/msm: update generated headers
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Resync generated headers to pull in a6xx registers.
Signed-off-by: Rob Clark <robdclark@gmail.com >
2018-08-10 18:49:18 -04:00
