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https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git
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d8ab94fa43
i.MX95 features a Cortex-M33 core, six Cortex-A55 cores, and
one Cortex-M7 core. The System Control Management Interface(SCMI)
firmware runs on the M33 core. The i.MX95 SCMI firmware named System
Manager(SM) includes vendor extension protocols, Logical Machine
Management(LMM) protocol and CPU protocol and etc.
Depending on SM configuration, M7 can be used as follows:
(1) M7 in a separate Logical Machine (LM) from A55 cores, that Linux
can't control
(2) M7 in a separate LM from A55 cores that Linux can control using LMM
protocol.
(3) M7 runs in same Logical Machine as A55 cores, so Linux can control it
using CPU protocol
So extend the driver to using LMM and CPU protocol to manage the M7 core.
- Compare linux LM ID(got using scmi_imx_lmm_info) and M7 LM ID(the ID
is fixed as 1 in SM firmware if M7 is in a separate LM),
if Linux LM ID is not same as M7 LM ID(linux and M7 in same LM), use
LMM protocol to start/stop. CPU protocol support will be added in the
following patch. Whether using CPU or LMM protocol to start/stop, the
M7 status detection could use CPU protocol to detect started or not. So
in imx_rproc_detect_mode, use scmi_imx_cpu_started to check the
status of M7.
- For above case (1) and (2), Use SCMI_IMX_LMM_POWER_ON to detect whether
the M7 LM is under control of A55 LM.
- For above case , after using SCMI_IMX_LMM_POWER_ON to check
permission, SCMI_IMX_LMM_SHUTDOWN API should be called to shutdown
the M7 LM to save power only when M7 LM is going to be started by
remoteproc framework. Otherwise bypass SCMI_IMX_LMM_SHUTDOWN API if
M7 LM is started before booting Linux.
Current setup relies on pre-Linux software(U-Boot) to do M7 TCM ECC
initialization. In future, we could add the support in Linux to decouple
U-Boot and Linux.
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20260109-imx95-rproc-2026-1-8-v6-4-d2fefb36263d@nxp.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
47 lines
1.1 KiB
C
47 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2017 Pengutronix, Oleksij Rempel <kernel@pengutronix.de>
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* Copyright 2021 NXP
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*/
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#ifndef _IMX_RPROC_H
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#define _IMX_RPROC_H
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/* address translation table */
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struct imx_rproc_att {
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u32 da; /* device address (From Cortex M4 view)*/
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u32 sa; /* system bus address */
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u32 size; /* size of reg range */
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int flags;
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};
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/* dcfg flags */
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#define IMX_RPROC_NEED_SYSTEM_OFF BIT(0)
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#define IMX_RPROC_NEED_CLKS BIT(1)
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struct imx_rproc_plat_ops {
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int (*start)(struct rproc *rproc);
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int (*stop)(struct rproc *rproc);
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int (*detach)(struct rproc *rproc);
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int (*detect_mode)(struct rproc *rproc);
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int (*prepare)(struct rproc *rproc);
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};
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struct imx_rproc_dcfg {
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u32 src_reg;
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u32 src_mask;
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u32 src_start;
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u32 src_stop;
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u32 gpr_reg;
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u32 gpr_wait;
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const struct imx_rproc_att *att;
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size_t att_size;
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u32 flags;
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const struct imx_rproc_plat_ops *ops;
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/* For System Manager(SM) based SoCs */
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u32 cpuid; /* ID of the remote core */
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u32 lmid; /* ID of the Logcial Machine */
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};
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#endif /* _IMX_RPROC_H */
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