mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git
synced 2026-04-18 03:23:53 -04:00
0892c91b81
Move the PowerPC SPE AES assembly code into lib/crypto/, wire the key expansion and single-block en/decryption functions up to the AES library API, and remove the superseded "aes-ppc-spe" crypto_cipher algorithm. The result is that both the AES library and crypto_cipher APIs are now optimized with SPE, whereas previously only crypto_cipher was (and optimizations weren't enabled by default, which this commit fixes too). Note that many of the functions in the PowerPC SPE assembly code are still used by the AES mode implementations in arch/powerpc/crypto/. For now, just export these functions. These exports will go away once the AES modes are migrated to the library as well. (Trying to split up the assembly files seemed like much more trouble than it would be worth.) Acked-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20260112192035.10427-13-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org>
347 lines
7.5 KiB
ArmAsm
347 lines
7.5 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Fast AES implementation for SPE instruction set (PPC)
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*
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* This code makes use of the SPE SIMD instruction set as defined in
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* http://cache.freescale.com/files/32bit/doc/ref_manual/SPEPIM.pdf
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* Implementation is based on optimization guide notes from
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* http://cache.freescale.com/files/32bit/doc/app_note/AN2665.pdf
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*
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* Copyright (c) 2015 Markus Stockhausen <stockhausen@collogia.de>
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*/
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#include <asm/ppc_asm.h>
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#include "aes-spe-regs.h"
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#define EAD(in, bpos) \
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rlwimi rT0,in,28-((bpos+3)%4)*8,20,27;
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#define DAD(in, bpos) \
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rlwimi rT1,in,24-((bpos+3)%4)*8,24,31;
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#define LWH(out, off) \
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evlwwsplat out,off(rT0); /* load word high */
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#define LWL(out, off) \
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lwz out,off(rT0); /* load word low */
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#define LBZ(out, tab, off) \
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lbz out,off(tab); /* load byte */
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#define LAH(out, in, bpos, off) \
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EAD(in, bpos) /* calc addr + load word high */ \
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LWH(out, off)
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#define LAL(out, in, bpos, off) \
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EAD(in, bpos) /* calc addr + load word low */ \
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LWL(out, off)
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#define LAE(out, in, bpos) \
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EAD(in, bpos) /* calc addr + load enc byte */ \
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LBZ(out, rT0, 8)
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#define LBE(out) \
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LBZ(out, rT0, 8) /* load enc byte */
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#define LAD(out, in, bpos) \
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DAD(in, bpos) /* calc addr + load dec byte */ \
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LBZ(out, rT1, 0)
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#define LBD(out) \
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LBZ(out, rT1, 0)
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/*
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* ppc_encrypt_block: The central encryption function for a single 16 bytes
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* block. It does no stack handling or register saving to support fast calls
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* via bl/blr. It expects that caller has pre-xored input data with first
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* 4 words of encryption key into rD0-rD3. Pointer/counter registers must
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* have also been set up before (rT0, rKP, CTR). Output is stored in rD0-rD3
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* and rW0-rW3 and caller must execute a final xor on the output registers.
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* All working registers rD0-rD3 & rW0-rW7 are overwritten during processing.
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*
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*/
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_GLOBAL(ppc_encrypt_block)
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LAH(rW4, rD1, 2, 4)
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LAH(rW6, rD0, 3, 0)
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LAH(rW3, rD0, 1, 8)
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ppc_encrypt_block_loop:
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LAH(rW0, rD3, 0, 12)
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LAL(rW0, rD0, 0, 12)
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LAH(rW1, rD1, 0, 12)
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LAH(rW2, rD2, 1, 8)
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LAL(rW2, rD3, 1, 8)
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LAL(rW3, rD1, 1, 8)
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LAL(rW4, rD2, 2, 4)
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LAL(rW6, rD1, 3, 0)
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LAH(rW5, rD3, 2, 4)
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LAL(rW5, rD0, 2, 4)
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LAH(rW7, rD2, 3, 0)
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evldw rD1,16(rKP)
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EAD(rD3, 3)
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evxor rW2,rW2,rW4
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LWL(rW7, 0)
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evxor rW2,rW2,rW6
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EAD(rD2, 0)
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evxor rD1,rD1,rW2
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LWL(rW1, 12)
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evxor rD1,rD1,rW0
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evldw rD3,24(rKP)
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evmergehi rD0,rD0,rD1
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EAD(rD1, 2)
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evxor rW3,rW3,rW5
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LWH(rW4, 4)
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evxor rW3,rW3,rW7
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EAD(rD0, 3)
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evxor rD3,rD3,rW3
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LWH(rW6, 0)
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evxor rD3,rD3,rW1
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EAD(rD0, 1)
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evmergehi rD2,rD2,rD3
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LWH(rW3, 8)
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LAH(rW0, rD3, 0, 12)
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LAL(rW0, rD0, 0, 12)
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LAH(rW1, rD1, 0, 12)
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LAH(rW2, rD2, 1, 8)
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LAL(rW2, rD3, 1, 8)
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LAL(rW3, rD1, 1, 8)
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LAL(rW4, rD2, 2, 4)
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LAL(rW6, rD1, 3, 0)
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LAH(rW5, rD3, 2, 4)
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LAL(rW5, rD0, 2, 4)
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LAH(rW7, rD2, 3, 0)
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evldw rD1,32(rKP)
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EAD(rD3, 3)
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evxor rW2,rW2,rW4
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LWL(rW7, 0)
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evxor rW2,rW2,rW6
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EAD(rD2, 0)
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evxor rD1,rD1,rW2
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LWL(rW1, 12)
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evxor rD1,rD1,rW0
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evldw rD3,40(rKP)
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evmergehi rD0,rD0,rD1
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EAD(rD1, 2)
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evxor rW3,rW3,rW5
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LWH(rW4, 4)
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evxor rW3,rW3,rW7
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EAD(rD0, 3)
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evxor rD3,rD3,rW3
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LWH(rW6, 0)
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evxor rD3,rD3,rW1
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EAD(rD0, 1)
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evmergehi rD2,rD2,rD3
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LWH(rW3, 8)
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addi rKP,rKP,32
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bdnz ppc_encrypt_block_loop
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LAH(rW0, rD3, 0, 12)
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LAL(rW0, rD0, 0, 12)
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LAH(rW1, rD1, 0, 12)
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LAH(rW2, rD2, 1, 8)
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LAL(rW2, rD3, 1, 8)
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LAL(rW3, rD1, 1, 8)
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LAL(rW4, rD2, 2, 4)
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LAH(rW5, rD3, 2, 4)
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LAL(rW6, rD1, 3, 0)
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LAL(rW5, rD0, 2, 4)
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LAH(rW7, rD2, 3, 0)
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evldw rD1,16(rKP)
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EAD(rD3, 3)
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evxor rW2,rW2,rW4
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LWL(rW7, 0)
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evxor rW2,rW2,rW6
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EAD(rD2, 0)
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evxor rD1,rD1,rW2
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LWL(rW1, 12)
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evxor rD1,rD1,rW0
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evldw rD3,24(rKP)
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evmergehi rD0,rD0,rD1
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EAD(rD1, 0)
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evxor rW3,rW3,rW5
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LBE(rW2)
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evxor rW3,rW3,rW7
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EAD(rD0, 1)
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evxor rD3,rD3,rW3
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LBE(rW6)
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evxor rD3,rD3,rW1
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EAD(rD0, 0)
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evmergehi rD2,rD2,rD3
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LBE(rW1)
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LAE(rW0, rD3, 0)
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LAE(rW1, rD0, 0)
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LAE(rW4, rD2, 1)
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LAE(rW5, rD3, 1)
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LAE(rW3, rD2, 0)
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LAE(rW7, rD1, 1)
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rlwimi rW0,rW4,8,16,23
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rlwimi rW1,rW5,8,16,23
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LAE(rW4, rD1, 2)
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LAE(rW5, rD2, 2)
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rlwimi rW2,rW6,8,16,23
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rlwimi rW3,rW7,8,16,23
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LAE(rW6, rD3, 2)
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LAE(rW7, rD0, 2)
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rlwimi rW0,rW4,16,8,15
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rlwimi rW1,rW5,16,8,15
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LAE(rW4, rD0, 3)
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LAE(rW5, rD1, 3)
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rlwimi rW2,rW6,16,8,15
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lwz rD0,32(rKP)
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rlwimi rW3,rW7,16,8,15
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lwz rD1,36(rKP)
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LAE(rW6, rD2, 3)
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LAE(rW7, rD3, 3)
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rlwimi rW0,rW4,24,0,7
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lwz rD2,40(rKP)
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rlwimi rW1,rW5,24,0,7
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lwz rD3,44(rKP)
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rlwimi rW2,rW6,24,0,7
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rlwimi rW3,rW7,24,0,7
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blr
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/*
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* ppc_decrypt_block: The central decryption function for a single 16 bytes
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* block. It does no stack handling or register saving to support fast calls
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* via bl/blr. It expects that caller has pre-xored input data with first
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* 4 words of encryption key into rD0-rD3. Pointer/counter registers must
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* have also been set up before (rT0, rKP, CTR). Output is stored in rD0-rD3
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* and rW0-rW3 and caller must execute a final xor on the output registers.
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* All working registers rD0-rD3 & rW0-rW7 are overwritten during processing.
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*
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*/
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_GLOBAL(ppc_decrypt_block)
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LAH(rW0, rD1, 0, 12)
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LAH(rW6, rD0, 3, 0)
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LAH(rW3, rD0, 1, 8)
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ppc_decrypt_block_loop:
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LAH(rW1, rD3, 0, 12)
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LAL(rW0, rD2, 0, 12)
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LAH(rW2, rD2, 1, 8)
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LAL(rW2, rD3, 1, 8)
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LAH(rW4, rD3, 2, 4)
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LAL(rW4, rD0, 2, 4)
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LAL(rW6, rD1, 3, 0)
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LAH(rW5, rD1, 2, 4)
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LAH(rW7, rD2, 3, 0)
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LAL(rW7, rD3, 3, 0)
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LAL(rW3, rD1, 1, 8)
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evldw rD1,16(rKP)
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EAD(rD0, 0)
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evxor rW4,rW4,rW6
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LWL(rW1, 12)
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evxor rW0,rW0,rW4
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EAD(rD2, 2)
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evxor rW0,rW0,rW2
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LWL(rW5, 4)
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evxor rD1,rD1,rW0
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evldw rD3,24(rKP)
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evmergehi rD0,rD0,rD1
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EAD(rD1, 0)
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evxor rW3,rW3,rW7
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LWH(rW0, 12)
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evxor rW3,rW3,rW1
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EAD(rD0, 3)
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evxor rD3,rD3,rW3
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LWH(rW6, 0)
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evxor rD3,rD3,rW5
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EAD(rD0, 1)
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evmergehi rD2,rD2,rD3
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LWH(rW3, 8)
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LAH(rW1, rD3, 0, 12)
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LAL(rW0, rD2, 0, 12)
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LAH(rW2, rD2, 1, 8)
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LAL(rW2, rD3, 1, 8)
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LAH(rW4, rD3, 2, 4)
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LAL(rW4, rD0, 2, 4)
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LAL(rW6, rD1, 3, 0)
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LAH(rW5, rD1, 2, 4)
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LAH(rW7, rD2, 3, 0)
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LAL(rW7, rD3, 3, 0)
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LAL(rW3, rD1, 1, 8)
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evldw rD1,32(rKP)
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EAD(rD0, 0)
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evxor rW4,rW4,rW6
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LWL(rW1, 12)
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evxor rW0,rW0,rW4
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EAD(rD2, 2)
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evxor rW0,rW0,rW2
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LWL(rW5, 4)
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evxor rD1,rD1,rW0
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evldw rD3,40(rKP)
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evmergehi rD0,rD0,rD1
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EAD(rD1, 0)
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evxor rW3,rW3,rW7
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LWH(rW0, 12)
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evxor rW3,rW3,rW1
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EAD(rD0, 3)
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evxor rD3,rD3,rW3
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LWH(rW6, 0)
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evxor rD3,rD3,rW5
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EAD(rD0, 1)
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evmergehi rD2,rD2,rD3
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LWH(rW3, 8)
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addi rKP,rKP,32
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bdnz ppc_decrypt_block_loop
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LAH(rW1, rD3, 0, 12)
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LAL(rW0, rD2, 0, 12)
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LAH(rW2, rD2, 1, 8)
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LAL(rW2, rD3, 1, 8)
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LAH(rW4, rD3, 2, 4)
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LAL(rW4, rD0, 2, 4)
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LAL(rW6, rD1, 3, 0)
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LAH(rW5, rD1, 2, 4)
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LAH(rW7, rD2, 3, 0)
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LAL(rW7, rD3, 3, 0)
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LAL(rW3, rD1, 1, 8)
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evldw rD1,16(rKP)
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EAD(rD0, 0)
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evxor rW4,rW4,rW6
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LWL(rW1, 12)
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evxor rW0,rW0,rW4
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EAD(rD2, 2)
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evxor rW0,rW0,rW2
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LWL(rW5, 4)
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evxor rD1,rD1,rW0
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evldw rD3,24(rKP)
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evmergehi rD0,rD0,rD1
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DAD(rD1, 0)
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evxor rW3,rW3,rW7
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LBD(rW0)
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evxor rW3,rW3,rW1
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DAD(rD0, 1)
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evxor rD3,rD3,rW3
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LBD(rW6)
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evxor rD3,rD3,rW5
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DAD(rD0, 0)
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evmergehi rD2,rD2,rD3
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LBD(rW3)
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LAD(rW2, rD3, 0)
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LAD(rW1, rD2, 0)
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LAD(rW4, rD2, 1)
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LAD(rW5, rD3, 1)
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LAD(rW7, rD1, 1)
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rlwimi rW0,rW4,8,16,23
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rlwimi rW1,rW5,8,16,23
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LAD(rW4, rD3, 2)
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LAD(rW5, rD0, 2)
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rlwimi rW2,rW6,8,16,23
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rlwimi rW3,rW7,8,16,23
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LAD(rW6, rD1, 2)
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LAD(rW7, rD2, 2)
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rlwimi rW0,rW4,16,8,15
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rlwimi rW1,rW5,16,8,15
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LAD(rW4, rD0, 3)
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LAD(rW5, rD1, 3)
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rlwimi rW2,rW6,16,8,15
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lwz rD0,32(rKP)
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rlwimi rW3,rW7,16,8,15
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lwz rD1,36(rKP)
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LAD(rW6, rD2, 3)
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LAD(rW7, rD3, 3)
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rlwimi rW0,rW4,24,0,7
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lwz rD2,40(rKP)
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rlwimi rW1,rW5,24,0,7
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lwz rD3,44(rKP)
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rlwimi rW2,rW6,24,0,7
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rlwimi rW3,rW7,24,0,7
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blr
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