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https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git
synced 2026-04-18 03:23:53 -04:00
0892c91b81
Move the PowerPC SPE AES assembly code into lib/crypto/, wire the key expansion and single-block en/decryption functions up to the AES library API, and remove the superseded "aes-ppc-spe" crypto_cipher algorithm. The result is that both the AES library and crypto_cipher APIs are now optimized with SPE, whereas previously only crypto_cipher was (and optimizations weren't enabled by default, which this commit fixes too). Note that many of the functions in the PowerPC SPE assembly code are still used by the AES mode implementations in arch/powerpc/crypto/. For now, just export these functions. These exports will go away once the AES modes are migrated to the library as well. (Trying to split up the assembly files seemed like much more trouble than it would be worth.) Acked-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20260112192035.10427-13-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org>
38 lines
1.1 KiB
C
38 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Common registers for PPC AES implementation
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*
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* Copyright (c) 2015 Markus Stockhausen <stockhausen@collogia.de>
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*/
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#define rKS r0 /* copy of en-/decryption key pointer */
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#define rDP r3 /* destination pointer */
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#define rSP r4 /* source pointer */
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#define rKP r5 /* pointer to en-/decryption key pointer */
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#define rRR r6 /* en-/decryption rounds */
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#define rLN r7 /* length of data to be processed */
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#define rIP r8 /* potiner to IV (CBC/CTR/XTS modes) */
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#define rKT r9 /* pointer to tweak key (XTS mode) */
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#define rT0 r11 /* pointers to en-/decryption tables */
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#define rT1 r10
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#define rD0 r9 /* data */
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#define rD1 r14
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#define rD2 r12
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#define rD3 r15
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#define rW0 r16 /* working registers */
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#define rW1 r17
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#define rW2 r18
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#define rW3 r19
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#define rW4 r20
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#define rW5 r21
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#define rW6 r22
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#define rW7 r23
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#define rI0 r24 /* IV */
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#define rI1 r25
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#define rI2 r26
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#define rI3 r27
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#define rG0 r28 /* endian reversed tweak (XTS mode) */
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#define rG1 r29
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#define rG2 r30
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#define rG3 r31
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