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https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git
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85cedb4e0c
Add device tree bindings for display clock controller on QCM2290 SoCs. Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1644432308-21099-1-git-send-email-loic.poulain@linaro.org
88 lines
2.3 KiB
YAML
88 lines
2.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,qcm2290-dispcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock & Reset Controller Binding for qcm2290
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maintainers:
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- Loic Poulain <loic.poulain@linaro.org>
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description: |
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Qualcomm display clock control module which supports the clocks, resets and
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power domains on qcm2290.
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See also dt-bindings/clock/qcom,dispcc-qcm2290.h.
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properties:
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compatible:
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const: qcom,qcm2290-dispcc
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clocks:
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items:
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- description: Board XO source
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- description: Board active-only XO source
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- description: GPLL0 source from GCC
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- description: GPLL0 div source from GCC
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- description: Byte clock from DSI PHY
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- description: Pixel clock from DSI PHY
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clock-names:
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items:
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- const: bi_tcxo
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- const: bi_tcxo_ao
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- const: gcc_disp_gpll0_clk_src
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- const: gcc_disp_gpll0_div_clk_src
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- const: dsi0_phy_pll_out_byteclk
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- const: dsi0_phy_pll_out_dsiclk
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
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#include <dt-bindings/clock/qcom,gcc-qcm2290.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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clock-controller@5f00000 {
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compatible = "qcom,qcm2290-dispcc";
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reg = <0x5f00000 0x20000>;
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
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<&rpmcc RPM_SMD_XO_A_CLK_SRC>,
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<&gcc GCC_DISP_GPLL0_CLK_SRC>,
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<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
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<&dsi0_phy 0>,
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<&dsi0_phy 1>;
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clock-names = "bi_tcxo",
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"bi_tcxo_ao",
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"gcc_disp_gpll0_clk_src",
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"gcc_disp_gpll0_div_clk_src",
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"dsi0_phy_pll_out_byteclk",
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"dsi0_phy_pll_out_dsiclk";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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