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https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git
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369eb4aaae
The arbiter configuration, the offset to the arbiter config CSR and the offset to the worker thread to service arbiter CSR are going to be different in QAT GEN4 devices although the logic that uses them is the same across all QAT generations. This patch reworks the gen-specific parts of the arbiter access code by introducing the arb_info structure, that contains the values that are generation specific, and a function in the structure adf_hw_device_data, get_arb_info(), that allows to get them. Since the arbiter values for QAT GEN2 devices (c62x, c3xxx and dh895xcc) are the same, a single function, adf_gen2_get_arb_info() is provided in adf_gen2_hw_data.c and referenced by each QAT GEN2 driver. Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Fiona Trahe <fiona.trahe@intel.com> Reviewed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
112 lines
4.7 KiB
C
112 lines
4.7 KiB
C
/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
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/* Copyright(c) 2020 Intel Corporation */
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#ifndef ADF_GEN2_HW_DATA_H_
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#define ADF_GEN2_HW_DATA_H_
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#include "adf_accel_devices.h"
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/* Transport access */
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#define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL
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#define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL
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#define ADF_RING_CSR_RING_CONFIG 0x000
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#define ADF_RING_CSR_RING_LBASE 0x040
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#define ADF_RING_CSR_RING_UBASE 0x080
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#define ADF_RING_CSR_RING_HEAD 0x0C0
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#define ADF_RING_CSR_RING_TAIL 0x100
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#define ADF_RING_CSR_E_STAT 0x14C
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#define ADF_RING_CSR_INT_FLAG 0x170
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#define ADF_RING_CSR_INT_SRCSEL 0x174
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#define ADF_RING_CSR_INT_SRCSEL_2 0x178
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#define ADF_RING_CSR_INT_COL_EN 0x17C
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#define ADF_RING_CSR_INT_COL_CTL 0x180
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#define ADF_RING_CSR_INT_FLAG_AND_COL 0x184
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#define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000
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#define ADF_RING_BUNDLE_SIZE 0x1000
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#define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \
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ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
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ADF_RING_CSR_RING_HEAD + ((ring) << 2))
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#define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \
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ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
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ADF_RING_CSR_RING_TAIL + ((ring) << 2))
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#define READ_CSR_E_STAT(csr_base_addr, bank) \
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ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
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ADF_RING_CSR_E_STAT)
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#define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \
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ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
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ADF_RING_CSR_RING_CONFIG + ((ring) << 2), value)
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#define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \
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do { \
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u32 l_base = 0, u_base = 0; \
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l_base = (u32)((value) & 0xFFFFFFFF); \
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u_base = (u32)(((value) & 0xFFFFFFFF00000000ULL) >> 32); \
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ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
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ADF_RING_CSR_RING_LBASE + ((ring) << 2), l_base); \
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ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
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ADF_RING_CSR_RING_UBASE + ((ring) << 2), u_base); \
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} while (0)
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#define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \
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ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
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ADF_RING_CSR_RING_HEAD + ((ring) << 2), value)
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#define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \
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ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
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ADF_RING_CSR_RING_TAIL + ((ring) << 2), value)
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#define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \
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ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
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ADF_RING_CSR_INT_FLAG, value)
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#define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \
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do { \
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ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
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ADF_RING_CSR_INT_SRCSEL, ADF_BANK_INT_SRC_SEL_MASK_0); \
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ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
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ADF_RING_CSR_INT_SRCSEL_2, ADF_BANK_INT_SRC_SEL_MASK_X); \
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} while (0)
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#define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \
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ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
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ADF_RING_CSR_INT_COL_EN, value)
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#define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \
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ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
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ADF_RING_CSR_INT_COL_CTL, \
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ADF_RING_CSR_INT_COL_CTL_ENABLE | (value))
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#define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \
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ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
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ADF_RING_CSR_INT_FLAG_AND_COL, value)
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/* AE to function map */
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#define AE2FUNCTION_MAP_A_OFFSET (0x3A400 + 0x190)
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#define AE2FUNCTION_MAP_B_OFFSET (0x3A400 + 0x310)
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#define AE2FUNCTION_MAP_REG_SIZE 4
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#define AE2FUNCTION_MAP_VALID BIT(7)
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#define READ_CSR_AE2FUNCTION_MAP_A(pmisc_bar_addr, index) \
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ADF_CSR_RD(pmisc_bar_addr, AE2FUNCTION_MAP_A_OFFSET + \
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AE2FUNCTION_MAP_REG_SIZE * (index))
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#define WRITE_CSR_AE2FUNCTION_MAP_A(pmisc_bar_addr, index, value) \
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ADF_CSR_WR(pmisc_bar_addr, AE2FUNCTION_MAP_A_OFFSET + \
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AE2FUNCTION_MAP_REG_SIZE * (index), value)
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#define READ_CSR_AE2FUNCTION_MAP_B(pmisc_bar_addr, index) \
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ADF_CSR_RD(pmisc_bar_addr, AE2FUNCTION_MAP_B_OFFSET + \
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AE2FUNCTION_MAP_REG_SIZE * (index))
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#define WRITE_CSR_AE2FUNCTION_MAP_B(pmisc_bar_addr, index, value) \
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ADF_CSR_WR(pmisc_bar_addr, AE2FUNCTION_MAP_B_OFFSET + \
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AE2FUNCTION_MAP_REG_SIZE * (index), value)
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/* Admin Interface Offsets */
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#define ADF_ADMINMSGUR_OFFSET (0x3A000 + 0x574)
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#define ADF_ADMINMSGLR_OFFSET (0x3A000 + 0x578)
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#define ADF_MAILBOX_BASE_OFFSET 0x20970
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/* Arbiter configuration */
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#define ADF_ARB_OFFSET 0x30000
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#define ADF_ARB_WRK_2_SER_MAP_OFFSET 0x180
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#define ADF_ARB_CONFIG (BIT(31) | BIT(6) | BIT(0))
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void adf_gen2_cfg_iov_thds(struct adf_accel_dev *accel_dev, bool enable,
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int num_a_regs, int num_b_regs);
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void adf_gen2_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops);
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void adf_gen2_get_admin_info(struct admin_info *admin_csrs_info);
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void adf_gen2_get_arb_info(struct arb_info *arb_info);
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#endif
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