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00d9220ec5
The sram property was incorrectly added to the GMU binding when it
really belongs with the GPU binding instead. Let's go ahead and
move it.
While changes are being made here, let's update the sram property
description to mention that this property is only valid for a3xx and
a4xx GPUs. The a3xx/a4xx example in the GPU is replaced with what was
in the GMU.
Signed-off-by: Brian Masney <masneyb@onstation.org>
Fixes: 198a72c8f9 ("dt-bindings: display: msm: gmu: add optional ocmem property")
Acked-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
123 lines
3.7 KiB
Plaintext
123 lines
3.7 KiB
Plaintext
Qualcomm adreno/snapdragon GPU
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Required properties:
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- compatible: "qcom,adreno-XYZ.W", "qcom,adreno" or
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"amd,imageon-XYZ.W", "amd,imageon"
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for example: "qcom,adreno-306.0", "qcom,adreno"
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Note that you need to list the less specific "qcom,adreno" (since this
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is what the device is matched on), in addition to the more specific
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with the chip-id.
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If "amd,imageon" is used, there should be no top level msm device.
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The interrupt signal from the gpu.
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- clocks: device clocks (if applicable)
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See ../clocks/clock-bindings.txt for details.
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- clock-names: the following clocks are required by a3xx, a4xx and a5xx
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cores:
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* "core"
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* "iface"
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* "mem_iface"
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For GMU attached devices the GPU clocks are not used and are not required. The
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following devices should not list clocks:
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- qcom,adreno-630.2
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- iommus: optional phandle to an adreno iommu instance
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- operating-points-v2: optional phandle to the OPP operating points
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- interconnects: optional phandle to an interconnect provider. See
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../interconnect/interconnect.txt for details. Some A3xx and all A4xx platforms
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will have two paths; all others will have one path.
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- interconnect-names: The names of the interconnect paths that correspond to the
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interconnects property. Values must be gfx-mem and ocmem.
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- qcom,gmu: For GMU attached devices a phandle to the GMU device that will
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control the power for the GPU. Applicable targets:
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- qcom,adreno-630.2
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- zap-shader: For a5xx and a6xx devices this node contains a memory-region that
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points to reserved memory to store the zap shader that can be used to help
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bring the GPU out of secure mode.
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- firmware-name: optional property of the 'zap-shader' node, listing the
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relative path of the device specific zap firmware.
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- sram: phandle to the On Chip Memory (OCMEM) that's present on some a3xx and
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a4xx Snapdragon SoCs. See
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Documentation/devicetree/bindings/sram/qcom,ocmem.yaml.
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Example 3xx/4xx:
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/ {
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...
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gpu: adreno@fdb00000 {
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compatible = "qcom,adreno-330.2",
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"qcom,adreno";
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reg = <0xfdb00000 0x10000>;
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reg-names = "kgsl_3d0_reg_memory";
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "kgsl_3d0_irq";
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clock-names = "core",
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"iface",
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"mem_iface";
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clocks = <&mmcc OXILI_GFX3D_CLK>,
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<&mmcc OXILICX_AHB_CLK>,
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<&mmcc OXILICX_AXI_CLK>;
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sram = <&gpu_sram>;
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power-domains = <&mmcc OXILICX_GDSC>;
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operating-points-v2 = <&gpu_opp_table>;
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iommus = <&gpu_iommu 0>;
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};
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gpu_sram: ocmem@fdd00000 {
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compatible = "qcom,msm8974-ocmem";
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reg = <0xfdd00000 0x2000>,
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<0xfec00000 0x180000>;
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reg-names = "ctrl",
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"mem";
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clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
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<&mmcc OCMEMCX_OCMEMNOC_CLK>;
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clock-names = "core",
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"iface";
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#address-cells = <1>;
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#size-cells = <1>;
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gpu_sram: gpu-sram@0 {
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reg = <0x0 0x100000>;
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ranges = <0 0 0xfec00000 0x100000>;
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};
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};
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};
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Example a6xx (with GMU):
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/ {
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...
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gpu@5000000 {
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compatible = "qcom,adreno-630.2", "qcom,adreno";
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#stream-id-cells = <16>;
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reg = <0x5000000 0x40000>, <0x509e000 0x10>;
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reg-names = "kgsl_3d0_reg_memory", "cx_mem";
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/*
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* Look ma, no clocks! The GPU clocks and power are
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* controlled entirely by the GMU
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*/
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interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
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iommus = <&adreno_smmu 0>;
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operating-points-v2 = <&gpu_opp_table>;
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interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>;
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interconnect-names = "gfx-mem";
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qcom,gmu = <&gmu>;
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zap-shader {
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memory-region = <&zap_shader_region>;
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firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn"
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};
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};
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};
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