Xu, Jinze 430bb83dbd drm/amd/display: Reset fifo after enable otg ...

[Why]
In fast boot sequence, when change dispclk, otg is disabled but digfe
is enabled. This may cause dig fifo error.

[How]
Reset dig fifo after enable otg.

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: JinZe.Xu <JinZe.Xu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2021-11-22 14:45:01 -05:00

..

dcn30_afmt.c

drm/amd/display: Add VPG and AFMT low power support for DCN3.1

2021-09-14 15:57:11 -04:00

dcn30_afmt.h

drm/amd/display: Add VPG and AFMT low power support for DCN3.1

2021-09-14 15:57:11 -04:00

dcn30_cm_common.c

…

dcn30_cm_common.h

…

dcn30_dccg.c

drm/amd/display: Add interface for ADD & DROP PIXEL Registers

2021-06-08 12:22:42 -04:00

dcn30_dccg.h

drm/amd/display: Add interface for ADD & DROP PIXEL Registers

2021-06-08 12:22:42 -04:00

dcn30_dio_link_encoder.c

drm/amd/display: Add DP 2.0 BIOS and DMUB Support

2021-09-01 16:55:10 -04:00

dcn30_dio_link_encoder.h

…

dcn30_dio_stream_encoder.c

drm/amd/display: Reset fifo after enable otg

2021-11-22 14:45:01 -05:00

dcn30_dio_stream_encoder.h

drm/amd/display: Add interface to get Calibrated Avg Level from FIFO

2021-06-15 17:25:41 -04:00

dcn30_dpp_cm.c

drm/amd/display: Defer GAMCOR and DSCL power down sequence to vupdate

2021-10-28 14:26:15 -04:00

dcn30_dpp.c

drm/amd/display: Defer GAMCOR and DSCL power down sequence to vupdate

2021-10-28 14:26:15 -04:00

dcn30_dpp.h

drm/amd/display: Line Buffer changes

2021-07-23 10:07:58 -04:00

dcn30_dwb_cm.c

drm/amd/display: fix incorrect CM/TF programming sequence in dwb

2021-08-09 15:43:10 -04:00

dcn30_dwb.c

…

dcn30_dwb.h

…

dcn30_hubbub.c

drm/amd/display: log additional register state for debug

2021-07-21 13:39:25 -04:00

dcn30_hubbub.h

drm/amd/display: log additional register state for debug

2021-07-21 13:39:25 -04:00

dcn30_hubp.c

drm/amd/display: Use dcc_ind_blk value to set register directly

2021-09-23 15:17:28 -04:00

dcn30_hubp.h

…

dcn30_hwseq.c

drm/amd/display: Add helper for blanking all dp displays

2021-11-17 16:58:05 -05:00

dcn30_hwseq.h

…

dcn30_init.c

drm/amd/display: unblock abm when odm is enabled only on configs that support it

2021-09-14 15:57:09 -04:00

dcn30_init.h

…

dcn30_mmhubbub.c

…

dcn30_mmhubbub.h

…

dcn30_mpc.c

drm/amd/display: Add MPC meory shutdown support

2021-11-03 12:32:34 -04:00

dcn30_mpc.h

drm/amd/display: Initial DC support for Beige Goby

2021-05-19 22:42:00 -04:00

dcn30_opp.h

…

dcn30_optc.c

drm/amd/display: Fix issue with dynamic bpp change for DCN3x

2021-09-23 15:17:30 -04:00

dcn30_optc.h

drm/amd/display: Return last used DRR VTOTAL from DC

2021-06-08 12:20:12 -04:00

dcn30_resource.c

drm/amd/display: Revert changes for MPO underflow

2021-11-22 14:45:01 -05:00

dcn30_resource.h

drm/amd/display: Set min dcfclk if pipe count is 0

2021-09-01 16:55:10 -04:00

dcn30_vpg.c

drm/amd/display: Fix issue with dynamic bpp change for DCN3x

2021-09-23 15:17:30 -04:00

dcn30_vpg.h

drm/amd/display: Fix issue with dynamic bpp change for DCN3x

2021-09-23 15:17:30 -04:00

Makefile

…