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https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git
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57b1c0ef89
Multi-circular queue (MCQ) has been added in UFSHC v4.0 standard in addition to the Single Doorbell mode. The MCQ mode supports multiple submission and completion queues. Add support to allocate and configure the queues. Add module parameters support to configure the queues. Co-developed-by: Can Guo <quic_cang@quicinc.com> Signed-off-by: Can Guo <quic_cang@quicinc.com> Signed-off-by: Asutosh Das <quic_asutoshd@quicinc.com> Reviewed-by: Bart Van Assche <bvanassche@acm.org> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
125 lines
3.3 KiB
C
125 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022 Qualcomm Innovation Center. All rights reserved.
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*
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* Authors:
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* Asutosh Das <quic_asutoshd@quicinc.com>
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* Can Guo <quic_cang@quicinc.com>
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*/
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#include <asm/unaligned.h>
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#include <linux/dma-mapping.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include "ufshcd-priv.h"
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#define MAX_QUEUE_SUP GENMASK(7, 0)
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#define UFS_MCQ_MIN_RW_QUEUES 2
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#define UFS_MCQ_MIN_READ_QUEUES 0
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#define UFS_MCQ_NUM_DEV_CMD_QUEUES 1
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#define UFS_MCQ_MIN_POLL_QUEUES 0
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static int rw_queue_count_set(const char *val, const struct kernel_param *kp)
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{
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return param_set_uint_minmax(val, kp, UFS_MCQ_MIN_RW_QUEUES,
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num_possible_cpus());
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}
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static const struct kernel_param_ops rw_queue_count_ops = {
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.set = rw_queue_count_set,
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.get = param_get_uint,
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};
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static unsigned int rw_queues;
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module_param_cb(rw_queues, &rw_queue_count_ops, &rw_queues, 0644);
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MODULE_PARM_DESC(rw_queues,
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"Number of interrupt driven I/O queues used for rw. Default value is nr_cpus");
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static int read_queue_count_set(const char *val, const struct kernel_param *kp)
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{
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return param_set_uint_minmax(val, kp, UFS_MCQ_MIN_READ_QUEUES,
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num_possible_cpus());
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}
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static const struct kernel_param_ops read_queue_count_ops = {
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.set = read_queue_count_set,
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.get = param_get_uint,
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};
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static unsigned int read_queues;
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module_param_cb(read_queues, &read_queue_count_ops, &read_queues, 0644);
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MODULE_PARM_DESC(read_queues,
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"Number of interrupt driven read queues used for read. Default value is 0");
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static int poll_queue_count_set(const char *val, const struct kernel_param *kp)
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{
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return param_set_uint_minmax(val, kp, UFS_MCQ_MIN_POLL_QUEUES,
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num_possible_cpus());
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}
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static const struct kernel_param_ops poll_queue_count_ops = {
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.set = poll_queue_count_set,
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.get = param_get_uint,
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};
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static unsigned int poll_queues = 1;
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module_param_cb(poll_queues, &poll_queue_count_ops, &poll_queues, 0644);
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MODULE_PARM_DESC(poll_queues,
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"Number of poll queues used for r/w. Default value is 1");
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static int ufshcd_mcq_config_nr_queues(struct ufs_hba *hba)
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{
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int i;
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u32 hba_maxq, rem, tot_queues;
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struct Scsi_Host *host = hba->host;
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hba_maxq = FIELD_GET(MAX_QUEUE_SUP, hba->mcq_capabilities);
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tot_queues = UFS_MCQ_NUM_DEV_CMD_QUEUES + read_queues + poll_queues +
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rw_queues;
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if (hba_maxq < tot_queues) {
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dev_err(hba->dev, "Total queues (%d) exceeds HC capacity (%d)\n",
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tot_queues, hba_maxq);
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return -EOPNOTSUPP;
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}
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rem = hba_maxq - UFS_MCQ_NUM_DEV_CMD_QUEUES;
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if (rw_queues) {
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hba->nr_queues[HCTX_TYPE_DEFAULT] = rw_queues;
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rem -= hba->nr_queues[HCTX_TYPE_DEFAULT];
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} else {
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rw_queues = num_possible_cpus();
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}
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if (poll_queues) {
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hba->nr_queues[HCTX_TYPE_POLL] = poll_queues;
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rem -= hba->nr_queues[HCTX_TYPE_POLL];
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}
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if (read_queues) {
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hba->nr_queues[HCTX_TYPE_READ] = read_queues;
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rem -= hba->nr_queues[HCTX_TYPE_READ];
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}
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if (!hba->nr_queues[HCTX_TYPE_DEFAULT])
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hba->nr_queues[HCTX_TYPE_DEFAULT] = min3(rem, rw_queues,
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num_possible_cpus());
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for (i = 0; i < HCTX_MAX_TYPES; i++)
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host->nr_hw_queues += hba->nr_queues[i];
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hba->nr_hw_queues = host->nr_hw_queues + UFS_MCQ_NUM_DEV_CMD_QUEUES;
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return 0;
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}
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int ufshcd_mcq_init(struct ufs_hba *hba)
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{
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int ret;
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ret = ufshcd_mcq_config_nr_queues(hba);
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return ret;
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}
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