Peter De Schrijver 59af78d78d clk: tegra: Add SATA seq input control ...

This will be used by the powergating driver to ensure proper sequencer
state when the SATA domain is powergated.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

2017-03-20 14:26:03 +01:00

..

at91_pmc.h

clk: at91: pmc: drop at91_pmc_base

2016-02-17 17:53:03 +01:00

bcm2835.h

…

clk-conf.h

clk: Add missing header for 'bool' definition to clk-conf.h

2015-08-25 10:54:06 -07:00

mmp.h

clk: mmp: stop using platform headers

2015-12-01 21:44:22 +01:00

mxs.h

ARM: mxs: remove custom .init_time hook

2013-09-29 21:09:34 +02:00

renesas.h

clk: renesas: rcar-gen2: Remove obsolete rcar_gen2_clocks_init()

2016-11-02 20:44:20 +01:00

tegra.h

clk: tegra: Add SATA seq input control

2017-03-20 14:26:03 +01:00

ti.h

clk: ti: dpll: add support for specifying max rate for DPLLs

2016-04-15 17:26:18 -07:00

zynq.h

ARM: zynq: Map I/O memory on clkc init

2014-02-10 11:21:13 +01:00