mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git
synced 2026-04-23 14:02:06 -04:00
7083e14225
Update the AST2700 interrupt controller binding to match the actual
hardware and the irq-aspeed-intc driver behavior.
- Interrupts:
First-level INTC banks request multiple interrupt lines to the root
GIC, with a maximum of 10 per bank. Second-level INTC banks request
only one interrupt line to their parent INTC-IC. Therefore, set the
interrupts property to allow a minimum of 1 and a maximum of 10
entries.
- #interrupt-cells:
Set '#interrupt-cells' to <1> since the aspeed intc driver does not
support specifying a trigger type; only the interrupt index is used.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://patch.msgid.link/20251030060155.2342604-2-ryan_chen@aspeedtech.com
92 lines
2.9 KiB
YAML
92 lines
2.9 KiB
YAML
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Aspeed AST2700 Interrupt Controller
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description:
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This interrupt controller hardware is second level interrupt controller that
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is hooked to a parent interrupt controller. It's useful to combine multiple
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interrupt sources into 1 interrupt to parent interrupt controller.
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maintainers:
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- Kevin Chen <kevin_chen@aspeedtech.com>
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properties:
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compatible:
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enum:
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- aspeed,ast2700-intc-ic
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reg:
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maxItems: 1
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interrupt-controller: true
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'#interrupt-cells':
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const: 1
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description:
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The first cell is the IRQ number, the second cell is the trigger
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type as defined in interrupt.txt in this directory.
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interrupts:
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minItems: 1
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maxItems: 10
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description: |
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Depend to which INTC0 or INTC1 used.
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INTC0 and INTC1 are two kinds of interrupt controller with enable and raw
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status registers for use.
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INTC0 is used to assert GIC if interrupt in INTC1 asserted.
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INTC1 is used to assert INTC0 if interrupt of modules asserted.
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+-----+ +-------+ +---------+---module0
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| GIC |---| INTC0 |--+--| INTC1_0 |---module2
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| | | | | | |---...
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+-----+ +-------+ | +---------+---module31
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| +---------+---module0
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+---| INTC1_1 |---module2
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| | |---...
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| +---------+---module31
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...
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| +---------+---module0
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+---| INTC1_5 |---module2
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| |---...
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+---------+---module31
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required:
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- compatible
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- reg
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- interrupt-controller
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- '#interrupt-cells'
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- interrupts
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-controller@12101b00 {
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compatible = "aspeed,ast2700-intc-ic";
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reg = <0 0x12101b00 0 0x10>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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