Remington Brasga 3834ce3600 drm/amdgpu/uvd4: fix mask and shift definitions ...

A few define's are listed twice with different, incorrect values.
This fix sets them appropriately.

Signed-off-by: Remington Brasga <rbrasga@uci.edu>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2024-08-13 10:26:48 -04:00

..

uvd_3_1_d.h

…

uvd_3_1_sh_mask.h

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uvd_4_0_d.h

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uvd_4_0_sh_mask.h

drm/amdgpu/uvd4: fix mask and shift definitions

2024-08-13 10:26:48 -04:00

uvd_4_2_d.h

…

uvd_4_2_sh_mask.h

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uvd_5_0_d.h

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uvd_5_0_enum.h

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uvd_5_0_sh_mask.h

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uvd_6_0_d.h

…

uvd_6_0_enum.h

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uvd_6_0_sh_mask.h

…

uvd_7_0_offset.h

drm/amd/amdgpu: add mmUVD_FW_STATUS register to uvd700

2020-09-17 17:59:54 -04:00

uvd_7_0_sh_mask.h

drm/amd/amdgpu: add mmUVD_FW_STATUS register to uvd700

2020-09-17 17:59:54 -04:00