mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git
synced 2026-04-18 03:23:53 -04:00
0f920690a8
Add compatible string and property for the SiFive CLINT v2. The SiFive CLINT v2 is incompatible with the SiFive CLINT v0 due to differences in their control methods. Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250321083507.25298-1-nick.hu@sifive.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
105 lines
3.2 KiB
YAML
105 lines
3.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: SiFive Core Local Interruptor
|
|
|
|
maintainers:
|
|
- Palmer Dabbelt <palmer@dabbelt.com>
|
|
- Anup Patel <anup.patel@wdc.com>
|
|
|
|
description:
|
|
SiFive (and other RISC-V) SOCs include an implementation of the SiFive
|
|
Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
|
|
interrupts. It directly connects to the timer and inter-processor interrupt
|
|
lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
|
|
interrupt controller is the parent interrupt controller for CLINT device.
|
|
The clock frequency of CLINT is specified via "timebase-frequency" DT
|
|
property of "/cpus" DT node. The "timebase-frequency" DT property is
|
|
described in Documentation/devicetree/bindings/riscv/cpus.yaml
|
|
|
|
T-Head C906/C910 CPU cores include an implementation of CLINT too, however
|
|
their implementation lacks a memory-mapped MTIME register, thus not
|
|
compatible with SiFive ones.
|
|
|
|
properties:
|
|
compatible:
|
|
oneOf:
|
|
- items:
|
|
- enum:
|
|
- canaan,k210-clint # Canaan Kendryte K210
|
|
- sifive,fu540-c000-clint # SiFive FU540
|
|
- spacemit,k1-clint # SpacemiT K1
|
|
- starfive,jh7100-clint # StarFive JH7100
|
|
- starfive,jh7110-clint # StarFive JH7110
|
|
- starfive,jh8100-clint # StarFive JH8100
|
|
- const: sifive,clint0 # SiFive CLINT v0 IP block
|
|
- items:
|
|
- {}
|
|
- const: sifive,clint2 # SiFive CLINT v2 IP block
|
|
description:
|
|
SiFive CLINT v2 is the HRT that supports the Zicntr. The control of sifive,clint2
|
|
differs from that of sifive,clint0, making them incompatible.
|
|
- items:
|
|
- enum:
|
|
- allwinner,sun20i-d1-clint
|
|
- sophgo,cv1800b-clint
|
|
- sophgo,cv1812h-clint
|
|
- sophgo,sg2002-clint
|
|
- thead,th1520-clint
|
|
- const: thead,c900-clint
|
|
- items:
|
|
- const: sifive,clint0
|
|
- const: riscv,clint0
|
|
deprecated: true
|
|
description: For the QEMU virt machine only
|
|
|
|
description:
|
|
Should be "<vendor>,<chip>-clint", followed by "sifive,clint<version>"
|
|
when compatible with a SiFive CLINT. Please refer to
|
|
sifive-blocks-ip-versioning.txt for details regarding the latter.
|
|
|
|
reg:
|
|
maxItems: 1
|
|
|
|
interrupts-extended:
|
|
minItems: 1
|
|
maxItems: 4095
|
|
|
|
sifive,fine-ctr-bits:
|
|
maximum: 15
|
|
description: The width in bits of the fine counter.
|
|
|
|
if:
|
|
properties:
|
|
compatible:
|
|
contains:
|
|
const: sifive,clint2
|
|
then:
|
|
required:
|
|
- sifive,fine-ctr-bits
|
|
else:
|
|
properties:
|
|
sifive,fine-ctr-bits: false
|
|
|
|
additionalProperties: false
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
- interrupts-extended
|
|
|
|
examples:
|
|
- |
|
|
timer@2000000 {
|
|
compatible = "sifive,fu540-c000-clint", "sifive,clint0";
|
|
interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>,
|
|
<&cpu2intc 3>, <&cpu2intc 7>,
|
|
<&cpu3intc 3>, <&cpu3intc 7>,
|
|
<&cpu4intc 3>, <&cpu4intc 7>;
|
|
reg = <0x2000000 0x10000>;
|
|
};
|
|
...
|