mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git
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78964fcac4
[Why & How] Fix incomplete copyright notice in DC code. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
68 lines
2.1 KiB
C
68 lines
2.1 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright 2023 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DCN35_OPP_H
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#define __DCN35_OPP_H
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#include "dcn20/dcn20_opp.h"
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#define OPP_REG_VARIABLE_LIST_DCN3_5 \
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OPP_REG_VARIABLE_LIST_DCN2_0; \
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uint32_t OPP_TOP_CLK_CONTROL
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#define OPP_MASK_SH_LIST_DCN35(mask_sh) \
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OPP_MASK_SH_LIST_DCN20(mask_sh), \
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OPP_SF(OPP_TOP_CLK_CONTROL, OPP_FGCG_REP_DIS, mask_sh)
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#define OPP_DCN35_REG_FIELD_LIST(type) \
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struct { \
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OPP_DCN20_REG_FIELD_LIST(type); \
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type OPP_FGCG_REP_DIS; \
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}
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struct dcn35_opp_registers {
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OPP_REG_VARIABLE_LIST_DCN3_5;
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};
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struct dcn35_opp_shift {
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OPP_DCN35_REG_FIELD_LIST(uint8_t);
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};
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struct dcn35_opp_mask {
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OPP_DCN35_REG_FIELD_LIST(uint32_t);
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};
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void dcn35_opp_construct(struct dcn20_opp *oppn20,
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struct dc_context *ctx,
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uint32_t inst,
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const struct dcn35_opp_registers *regs,
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const struct dcn35_opp_shift *opp_shift,
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const struct dcn35_opp_mask *opp_mask);
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void dcn35_opp_set_fgcg(struct dcn20_opp *oppn20, bool enable);
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#endif
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