mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git
synced 2026-04-18 19:43:43 -04:00
3034cc8107
There's only one instance of the pcode per tile, and for GT-related
accesses both the primary and media GT share the same register
interface. Since Xe was using per-GT locking, the pcode mutex wasn't
actually protecting everything that it should since concurrent accesses
related to a tile's primary GT and media GT were possible.
Fixes: dd08ebf6c3 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240829220619.789159-5-matthew.d.roper@intel.com
43 lines
1.0 KiB
C
43 lines
1.0 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef __INTEL_PCODE_H__
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#define __INTEL_PCODE_H__
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#include "intel_uncore.h"
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#include "xe_pcode.h"
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static inline int
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snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,
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int fast_timeout_us, int slow_timeout_ms)
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{
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return xe_pcode_write_timeout(__compat_uncore_to_tile(uncore), mbox, val,
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slow_timeout_ms ?: 1);
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}
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static inline int
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snb_pcode_write(struct intel_uncore *uncore, u32 mbox, u32 val)
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{
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return xe_pcode_write(__compat_uncore_to_tile(uncore), mbox, val);
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}
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static inline int
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snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1)
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{
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return xe_pcode_read(__compat_uncore_to_tile(uncore), mbox, val, val1);
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}
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static inline int
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skl_pcode_request(struct intel_uncore *uncore, u32 mbox,
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u32 request, u32 reply_mask, u32 reply,
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int timeout_base_ms)
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{
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return xe_pcode_request(__compat_uncore_to_tile(uncore), mbox, request, reply_mask, reply,
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timeout_base_ms);
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}
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#endif /* __INTEL_PCODE_H__ */
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