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https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git
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7f2ef1bfc7
Add an adreno-smmu-priv interface for drm/msm to call into arm-smmu-qcom and initiate the "Partially Resident Region" (PRR) bit setup or reset sequence as per request. This will be used by GPU to setup the PRR bit and related configuration registers through adreno-smmu private interface instead of directly poking the smmu hardware. Suggested-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com> Link: https://lore.kernel.org/r/20241212151402.159102-4-quic_bibekkum@quicinc.com Signed-off-by: Will Deacon <will@kernel.org>
80 lines
3.2 KiB
C
80 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2020 Google, Inc
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*/
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#ifndef __ADRENO_SMMU_PRIV_H
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#define __ADRENO_SMMU_PRIV_H
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#include <linux/io-pgtable.h>
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/**
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* struct adreno_smmu_fault_info - container for key fault information
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*
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* @far: The faulting IOVA from ARM_SMMU_CB_FAR
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* @ttbr0: The current TTBR0 pagetable from ARM_SMMU_CB_TTBR0
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* @contextidr: The value of ARM_SMMU_CB_CONTEXTIDR
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* @fsr: The fault status from ARM_SMMU_CB_FSR
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* @fsynr0: The value of FSYNR0 from ARM_SMMU_CB_FSYNR0
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* @fsynr1: The value of FSYNR1 from ARM_SMMU_CB_FSYNR0
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* @cbfrsynra: The value of CBFRSYNRA from ARM_SMMU_GR1_CBFRSYNRA(idx)
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*
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* This struct passes back key page fault information to the GPU driver
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* through the get_fault_info function pointer.
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* The GPU driver can use this information to print informative
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* log messages and provide deeper GPU specific insight into the fault.
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*/
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struct adreno_smmu_fault_info {
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u64 far;
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u64 ttbr0;
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u32 contextidr;
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u32 fsr;
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u32 fsynr0;
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u32 fsynr1;
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u32 cbfrsynra;
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};
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/**
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* struct adreno_smmu_priv - private interface between adreno-smmu and GPU
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*
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* @cookie: An opque token provided by adreno-smmu and passed
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* back into the callbacks
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* @get_ttbr1_cfg: Get the TTBR1 config for the GPUs context-bank
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* @set_ttbr0_cfg: Set the TTBR0 config for the GPUs context bank. A
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* NULL config disables TTBR0 translation, otherwise
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* TTBR0 translation is enabled with the specified cfg
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* @get_fault_info: Called by the GPU fault handler to get information about
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* the fault
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* @set_stall: Configure whether stall on fault (CFCFG) is enabled. Call
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* before set_ttbr0_cfg(). If stalling on fault is enabled,
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* the GPU driver must call resume_translation()
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* @resume_translation: Resume translation after a fault
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*
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* @set_prr_bit: [optional] Configure the GPU's Partially Resident
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* Region (PRR) bit in the ACTLR register.
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* @set_prr_addr: [optional] Configure the PRR_CFG_*ADDR register with
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* the physical address of PRR page passed from GPU
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* driver.
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*
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* The GPU driver (drm/msm) and adreno-smmu work together for controlling
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* the GPU's SMMU instance. This is by necessity, as the GPU is directly
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* updating the SMMU for context switches, while on the other hand we do
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* not want to duplicate all of the initial setup logic from arm-smmu.
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*
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* This private interface is used for the two drivers to coordinate. The
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* cookie and callback functions are populated when the GPU driver attaches
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* it's domain.
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*/
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struct adreno_smmu_priv {
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const void *cookie;
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const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie);
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int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg);
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void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info);
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void (*set_stall)(const void *cookie, bool enabled);
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void (*resume_translation)(const void *cookie, bool terminate);
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void (*set_prr_bit)(const void *cookie, bool set);
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void (*set_prr_addr)(const void *cookie, phys_addr_t page_addr);
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};
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#endif /* __ADRENO_SMMU_PRIV_H */
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