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The PL011 IP has 2 clock inputs for UART core/baud and APB bus. The Thunder2 SoC is missing the core "uartclk". In this case, the Linux driver uses single clock for both clock inputs. Let's assume that's how the h/w is wired and make the DT reflect that. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250609215706.3009692-2-robh@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>