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9bc7130822
Introduce a new YAML schema for QUP-supported peripherals. Define common properties used across QUP-supported peripherals. Add property `qcom,enable-gsi-dma` to configure the Serial Engine (SE) for QCOM GPI DMA mode. Reference the common schema YAML in the GENI I2C, SPI, and SERIAL YAML files. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Co-developed-by: Mukesh Kumar Savaliya <mukesh.savaliya@oss.qualcomm.com> Signed-off-by: Mukesh Kumar Savaliya <mukesh.savaliya@oss.qualcomm.com> Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250911043256.3523057-2-viken.dadhaniya@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
88 lines
1.8 KiB
YAML
88 lines
1.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/serial/qcom,serial-geni-qcom.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Geni based QUP UART interface
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maintainers:
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- Andy Gross <agross@kernel.org>
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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allOf:
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- $ref: /schemas/serial/serial.yaml#
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- $ref: /schemas/soc/qcom/qcom,se-common-props.yaml#
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properties:
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compatible:
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enum:
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- qcom,geni-uart
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- qcom,geni-debug-uart
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clocks:
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maxItems: 1
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clock-names:
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const: se
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interconnects:
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maxItems: 2
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interconnect-names:
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items:
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- const: qup-core
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- const: qup-config
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interrupts:
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minItems: 1
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items:
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- description: UART core irq
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- description: Wakeup irq (RX GPIO)
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operating-points-v2: true
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pinctrl-0: true
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pinctrl-1: true
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pinctrl-names:
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minItems: 1
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items:
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- const: default
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- const: sleep
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power-domains:
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maxItems: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- clocks
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- clock-names
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- interrupts
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- reg
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-sc7180.h>
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#include <dt-bindings/interconnect/qcom,sc7180.h>
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serial@a88000 {
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compatible = "qcom,geni-uart";
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reg = <0xa88000 0x7000>;
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interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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pinctrl-0 = <&qup_uart0_default>;
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pinctrl-names = "default";
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interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
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<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
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interconnect-names = "qup-core", "qup-config";
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};
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...
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