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https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git
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b79c7532dc
QAT GEN2 devices share most of the behavior which means a number of device specific functions can be shared too and some differences abstracted away by simple parameters. The functions adf_enable_error_correction(), get_num_accels(), get_num_aes() and get_pf2vf_offset() for c3xxx, c62x and dh895xx have been reworked and moved to the GEN2 file, adf_gen2_hw_data.c. The definitions of tx_rx_gap and tx_rings_mask have been moved to adf_gen2_hw_data.h. Signed-off-by: Marco Chiappero <marco.chiappero@intel.com> Co-developed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
33 lines
1.1 KiB
C
33 lines
1.1 KiB
C
/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
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/* Copyright(c) 2014 - 2020 Intel Corporation */
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#ifndef ADF_C62X_HW_DATA_H_
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#define ADF_C62X_HW_DATA_H_
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/* PCIe configuration space */
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#define ADF_C62X_SRAM_BAR 0
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#define ADF_C62X_PMISC_BAR 1
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#define ADF_C62X_ETR_BAR 2
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#define ADF_C62X_MAX_ACCELERATORS 5
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#define ADF_C62X_MAX_ACCELENGINES 10
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#define ADF_C62X_ACCELERATORS_REG_OFFSET 16
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#define ADF_C62X_ACCELERATORS_MASK 0x1F
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#define ADF_C62X_ACCELENGINES_MASK 0x3FF
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#define ADF_C62X_ETR_MAX_BANKS 16
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#define ADF_C62X_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28)
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#define ADF_C62X_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30)
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#define ADF_C62X_SMIA0_MASK 0xFFFF
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#define ADF_C62X_SMIA1_MASK 0x1
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#define ADF_C62X_SOFTSTRAP_CSR_OFFSET 0x2EC
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/* AE to function mapping */
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#define ADF_C62X_AE2FUNC_MAP_GRP_A_NUM_REGS 80
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#define ADF_C62X_AE2FUNC_MAP_GRP_B_NUM_REGS 10
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/* Firmware Binary */
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#define ADF_C62X_FW "qat_c62x.bin"
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#define ADF_C62X_MMP "qat_c62x_mmp.bin"
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void adf_init_hw_data_c62x(struct adf_hw_device_data *hw_data);
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void adf_clean_hw_data_c62x(struct adf_hw_device_data *hw_data);
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#endif
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