mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git
synced 2026-04-23 05:56:14 -04:00
daaa75fd98
Teach Vega20 I2C to be agnostic. Allow addressing
different devices while the master holds the bus.
Set STOP as per the controller's specification.
v2: Qualify generating ReSTART before the 1st byte
of the message, when set by the caller, as
those functions are separated, as caught by
Andrey G.
Cc: Jean Delvare <jdelvare@suse.de>
Cc: Alexander Deucher <Alexander.Deucher@amd.com>
Cc: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Cc: Lijo Lazar <Lijo.Lazar@amd.com>
Cc: Stanley Yang <Stanley.Yang@amd.com>
Cc: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
Acked-by: Alexander Deucher <Alexander.Deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
83 lines
2.5 KiB
C
83 lines
2.5 KiB
C
/*
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* Copyright 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu_eeprom.h"
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#include "amdgpu.h"
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#define EEPROM_OFFSET_LENGTH 2
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int amdgpu_eeprom_xfer(struct i2c_adapter *i2c_adap,
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u16 slave_addr, u16 eeprom_addr,
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u8 *eeprom_buf, u16 bytes, bool read)
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{
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u8 eeprom_offset_buf[2];
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u16 bytes_transferred;
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struct i2c_msg msgs[] = {
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{
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.addr = slave_addr,
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.flags = 0,
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.len = EEPROM_OFFSET_LENGTH,
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.buf = eeprom_offset_buf,
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},
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{
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.addr = slave_addr,
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.flags = read ? I2C_M_RD : 0,
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.len = bytes,
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.buf = eeprom_buf,
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},
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};
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int r;
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msgs[0].buf[0] = ((eeprom_addr >> 8) & 0xff);
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msgs[0].buf[1] = (eeprom_addr & 0xff);
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while (msgs[1].len) {
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r = i2c_transfer(i2c_adap, msgs, ARRAY_SIZE(msgs));
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if (r <= 0)
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return r;
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/* Only for write data */
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if (!msgs[1].flags)
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/*
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* According to EEPROM spec there is a MAX of 10 ms required for
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* EEPROM to flush internal RX buffer after STOP was issued at the
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* end of write transaction. During this time the EEPROM will not be
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* responsive to any more commands - so wait a bit more.
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*
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* TODO Improve to wait for first ACK for slave address after
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* internal write cycle done.
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*/
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msleep(10);
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bytes_transferred = r - EEPROM_OFFSET_LENGTH;
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eeprom_addr += bytes_transferred;
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msgs[0].buf[0] = ((eeprom_addr >> 8) & 0xff);
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msgs[0].buf[1] = (eeprom_addr & 0xff);
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msgs[1].buf += bytes_transferred;
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msgs[1].len -= bytes_transferred;
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}
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return 0;
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}
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