mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git
synced 2026-04-19 03:53:51 -04:00
3034cc8107
There's only one instance of the pcode per tile, and for GT-related
accesses both the primary and media GT share the same register
interface. Since Xe was using per-GT locking, the pcode mutex wasn't
actually protecting everything that it should since concurrent accesses
related to a tile's primary GT and media GT were possible.
Fixes: dd08ebf6c3 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240829220619.789159-5-matthew.d.roper@intel.com
43 lines
1.0 KiB
C
43 lines
1.0 KiB
C
/* SPDX-License-Identifier: MIT */
|
|
/*
|
|
* Copyright © 2023 Intel Corporation
|
|
*/
|
|
|
|
#ifndef __INTEL_PCODE_H__
|
|
#define __INTEL_PCODE_H__
|
|
|
|
#include "intel_uncore.h"
|
|
#include "xe_pcode.h"
|
|
|
|
static inline int
|
|
snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,
|
|
int fast_timeout_us, int slow_timeout_ms)
|
|
{
|
|
return xe_pcode_write_timeout(__compat_uncore_to_tile(uncore), mbox, val,
|
|
slow_timeout_ms ?: 1);
|
|
}
|
|
|
|
static inline int
|
|
snb_pcode_write(struct intel_uncore *uncore, u32 mbox, u32 val)
|
|
{
|
|
|
|
return xe_pcode_write(__compat_uncore_to_tile(uncore), mbox, val);
|
|
}
|
|
|
|
static inline int
|
|
snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1)
|
|
{
|
|
return xe_pcode_read(__compat_uncore_to_tile(uncore), mbox, val, val1);
|
|
}
|
|
|
|
static inline int
|
|
skl_pcode_request(struct intel_uncore *uncore, u32 mbox,
|
|
u32 request, u32 reply_mask, u32 reply,
|
|
int timeout_base_ms)
|
|
{
|
|
return xe_pcode_request(__compat_uncore_to_tile(uncore), mbox, request, reply_mask, reply,
|
|
timeout_base_ms);
|
|
}
|
|
|
|
#endif /* __INTEL_PCODE_H__ */
|