mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git
synced 2026-04-18 03:23:53 -04:00
393e132efc
The gcc_aux_clk is not required by the PCIe PHY on qcs8300 and is not
specified in the device tree node. Hence, move the qcs8300 phy
compatibility entry into the list of PHYs that require six clocks.
Removed the phy_aux clock from the PCIe PHY binding as it is no longer
used by any instance.
Fixes: e46e59b77a ("dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the QCS8300 QMP PCIe PHY Gen4 x2")
Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://patch.msgid.link/20251128104928.4070050-2-ziyue.zhang@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
302 lines
7.9 KiB
YAML
302 lines
7.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
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maintainers:
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- Vinod Koul <vkoul@kernel.org>
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description:
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The QMP PHY controller supports physical layer functionality for a number of
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controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
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properties:
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compatible:
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enum:
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- qcom,glymur-qmp-gen5x4-pcie-phy
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- qcom,qcs615-qmp-gen3x1-pcie-phy
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- qcom,qcs8300-qmp-gen4x2-pcie-phy
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- qcom,sa8775p-qmp-gen4x2-pcie-phy
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- qcom,sa8775p-qmp-gen4x4-pcie-phy
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- qcom,sar2130p-qmp-gen3x2-pcie-phy
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- qcom,sc8180x-qmp-pcie-phy
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- qcom,sc8280xp-qmp-gen3x1-pcie-phy
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- qcom,sc8280xp-qmp-gen3x2-pcie-phy
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- qcom,sc8280xp-qmp-gen3x4-pcie-phy
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- qcom,sdm845-qhp-pcie-phy
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- qcom,sdm845-qmp-pcie-phy
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- qcom,sdx55-qmp-pcie-phy
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- qcom,sdx65-qmp-gen4x2-pcie-phy
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- qcom,sm8150-qmp-gen3x1-pcie-phy
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- qcom,sm8150-qmp-gen3x2-pcie-phy
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- qcom,sm8250-qmp-gen3x1-pcie-phy
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- qcom,sm8250-qmp-gen3x2-pcie-phy
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- qcom,sm8250-qmp-modem-pcie-phy
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- qcom,sm8350-qmp-gen3x1-pcie-phy
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- qcom,sm8350-qmp-gen3x2-pcie-phy
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- qcom,sm8450-qmp-gen3x1-pcie-phy
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- qcom,sm8450-qmp-gen4x2-pcie-phy
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- qcom,sm8550-qmp-gen3x2-pcie-phy
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- qcom,sm8550-qmp-gen4x2-pcie-phy
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- qcom,sm8650-qmp-gen3x2-pcie-phy
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- qcom,sm8650-qmp-gen4x2-pcie-phy
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- qcom,sm8750-qmp-gen3x2-pcie-phy
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- qcom,x1e80100-qmp-gen3x2-pcie-phy
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- qcom,x1e80100-qmp-gen4x2-pcie-phy
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- qcom,x1e80100-qmp-gen4x4-pcie-phy
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- qcom,x1e80100-qmp-gen4x8-pcie-phy
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- qcom,x1p42100-qmp-gen4x4-pcie-phy
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reg:
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minItems: 1
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maxItems: 2
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clocks:
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minItems: 5
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maxItems: 6
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clock-names:
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minItems: 5
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items:
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- const: aux
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- const: cfg_ahb
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- const: ref
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- enum: [rchng, refgen]
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- const: pipe
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- const: pipediv2
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power-domains:
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maxItems: 1
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resets:
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minItems: 1
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maxItems: 2
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reset-names:
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minItems: 1
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items:
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- const: phy
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- const: phy_nocsr
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vdda-phy-supply: true
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vdda-pll-supply: true
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vdda-qref-supply: true
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qcom,4ln-config-sel:
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description: PCIe 4-lane configuration
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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- items:
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- description: phandle of TCSR syscon
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- description: offset of PCIe 4-lane configuration register
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- description: offset of configuration bit for this PHY
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"#clock-cells": true
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clock-output-names:
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maxItems: 1
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"#phy-cells":
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const: 0
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- reset-names
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- vdda-phy-supply
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- vdda-pll-supply
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- "#clock-cells"
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- clock-output-names
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- "#phy-cells"
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additionalProperties: false
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sc8280xp-qmp-gen3x4-pcie-phy
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- qcom,x1e80100-qmp-gen4x4-pcie-phy
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- qcom,x1p42100-qmp-gen4x4-pcie-phy
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then:
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properties:
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reg:
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items:
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- description: port a
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- description: port b
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required:
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- qcom,4ln-config-sel
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else:
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properties:
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reg:
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maxItems: 1
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,qcs615-qmp-gen3x1-pcie-phy
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- qcom,sar2130p-qmp-gen3x2-pcie-phy
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- qcom,sc8180x-qmp-pcie-phy
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- qcom,sdm845-qhp-pcie-phy
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- qcom,sdm845-qmp-pcie-phy
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- qcom,sdx55-qmp-pcie-phy
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- qcom,sm8150-qmp-gen3x1-pcie-phy
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- qcom,sm8150-qmp-gen3x2-pcie-phy
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- qcom,sm8250-qmp-gen3x1-pcie-phy
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- qcom,sm8250-qmp-gen3x2-pcie-phy
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- qcom,sm8250-qmp-modem-pcie-phy
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- qcom,sm8350-qmp-gen3x1-pcie-phy
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- qcom,sm8350-qmp-gen3x2-pcie-phy
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- qcom,sm8450-qmp-gen3x1-pcie-phy
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- qcom,sm8450-qmp-gen3x2-pcie-phy
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- qcom,sm8550-qmp-gen3x2-pcie-phy
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- qcom,sm8550-qmp-gen4x2-pcie-phy
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- qcom,sm8650-qmp-gen3x2-pcie-phy
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- qcom,sm8650-qmp-gen4x2-pcie-phy
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- qcom,sm8750-qmp-gen3x2-pcie-phy
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then:
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properties:
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clocks:
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maxItems: 5
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clock-names:
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maxItems: 5
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,glymur-qmp-gen5x4-pcie-phy
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- qcom,qcs8300-qmp-gen4x2-pcie-phy
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- qcom,sa8775p-qmp-gen4x2-pcie-phy
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- qcom,sa8775p-qmp-gen4x4-pcie-phy
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- qcom,sc8280xp-qmp-gen3x1-pcie-phy
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- qcom,sc8280xp-qmp-gen3x2-pcie-phy
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- qcom,sc8280xp-qmp-gen3x4-pcie-phy
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- qcom,x1e80100-qmp-gen3x2-pcie-phy
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- qcom,x1e80100-qmp-gen4x2-pcie-phy
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- qcom,x1e80100-qmp-gen4x4-pcie-phy
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- qcom,x1e80100-qmp-gen4x8-pcie-phy
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- qcom,x1p42100-qmp-gen4x4-pcie-phy
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then:
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properties:
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clocks:
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minItems: 6
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clock-names:
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minItems: 6
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,glymur-qmp-gen5x4-pcie-phy
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- qcom,sm8550-qmp-gen4x2-pcie-phy
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- qcom,sm8650-qmp-gen4x2-pcie-phy
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- qcom,x1e80100-qmp-gen3x2-pcie-phy
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- qcom,x1e80100-qmp-gen4x2-pcie-phy
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- qcom,x1e80100-qmp-gen4x4-pcie-phy
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- qcom,x1e80100-qmp-gen4x8-pcie-phy
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- qcom,x1p42100-qmp-gen4x4-pcie-phy
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then:
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properties:
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resets:
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minItems: 2
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reset-names:
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minItems: 2
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else:
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properties:
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resets:
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maxItems: 1
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reset-names:
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maxItems: 1
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sm8450-qmp-gen4x2-pcie-phy
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- qcom,sm8550-qmp-gen4x2-pcie-phy
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- qcom,sm8650-qmp-gen4x2-pcie-phy
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then:
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properties:
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"#clock-cells":
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const: 1
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else:
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properties:
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"#clock-cells":
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const: 0
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
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pcie2b_phy: phy@1c18000 {
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compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
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reg = <0x01c18000 0x2000>;
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clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
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<&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
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<&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
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<&gcc GCC_PCIE_2B_PIPE_CLK>,
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<&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
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clock-names = "aux", "cfg_ahb", "ref", "rchng",
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"pipe", "pipediv2";
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power-domains = <&gcc PCIE_2B_GDSC>;
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resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
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reset-names = "phy";
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vdda-phy-supply = <&vreg_l6d>;
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vdda-pll-supply = <&vreg_l4d>;
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#clock-cells = <0>;
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clock-output-names = "pcie_2b_pipe_clk";
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#phy-cells = <0>;
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};
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pcie2a_phy: phy@1c24000 {
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compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
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reg = <0x01c24000 0x2000>, <0x01c26000 0x2000>;
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clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
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<&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
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<&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
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<&gcc GCC_PCIE_2A_PIPE_CLK>,
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<&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
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clock-names = "aux", "cfg_ahb", "ref", "rchng",
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"pipe", "pipediv2";
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power-domains = <&gcc PCIE_2A_GDSC>;
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resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
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reset-names = "phy";
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vdda-phy-supply = <&vreg_l6d>;
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vdda-pll-supply = <&vreg_l4d>;
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qcom,4ln-config-sel = <&tcsr 0xa044 0>;
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#clock-cells = <0>;
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clock-output-names = "pcie_2a_pipe_clk";
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#phy-cells = <0>;
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};
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