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ca677196a9
The Allwinner Power Reset Clock Management (RPCM) block contains a few bits that control some power domains. The most prominent one is the one for the Mali GPU. On the Allwinner H6 this domain is enabled at reset, so we didn't care about it so far, but the H616 defaults to it being disabled. Add a power domain driver for those bits. Some BSP code snippets and some spare documentation describe three bits, slightly different between the H6 and H616, so add three power domains for each SoC, connected to their compatible string. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Link: https://lore.kernel.org/r/20250416224839.9840-3-andre.przywara@arm.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
21 lines
642 B
Plaintext
21 lines
642 B
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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config SUN20I_PPU
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bool "Allwinner D1 PPU power domain driver"
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depends on ARCH_SUNXI || COMPILE_TEST
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depends on PM
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select PM_GENERIC_DOMAINS
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help
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Say y to enable the PPU power domain driver. This saves power
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when certain peripherals, such as the video engine, are idle.
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config SUN50I_H6_PRCM_PPU
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tristate "Allwinner H6 PRCM power domain driver"
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depends on ARCH_SUNXI || COMPILE_TEST
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depends on PM
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select PM_GENERIC_DOMAINS
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help
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Say y to enable the Allwinner H6/H616 PRCM power domain driver.
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This is required to enable the Mali GPU in the H616 SoC, it is
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optional for the H6.
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