Commit 00080d08 authored by Damien Le Moal's avatar Damien Le Moal Committed by Bjorn Helgaas
Browse files

PCI: rockship-ep: Implement the pci_epc_ops::stop_link() operation 

Define the EPC operation ->stop() for the Rockchip endpoint driver with
the function rockchip_pcie_ep_stop(). This function disables link
training and the controller configuration, as the reverse to what
the start operation defined with rockchip_pcie_ep_start() does.

Link: https://lore.kernel.org/r/20241017015849.190271-12-dlemoal@kernel.org


Signed-off-by: default avatarDamien Le Moal <dlemoal@kernel.org>
Signed-off-by: default avatarKrzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
parent 091022f5

drivers/pci/controller/pcie-rockchip-ep.c

+13 −0
Original line number Diff line number Diff line
@@ -476,6 +476,18 @@ static int rockchip_pcie_ep_start(struct pci_epc *epc) 
	return 0;

}



static void rockchip_pcie_ep_stop(struct pci_epc *epc)

{

	struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);

	struct rockchip_pcie *rockchip = &ep->rockchip;



	/* Stop link training and disable configuration */

	rockchip_pcie_write(rockchip,

			    PCIE_CLIENT_CONF_DISABLE |

			    PCIE_CLIENT_LINK_TRAIN_DISABLE,

			    PCIE_CLIENT_CONFIG);

}



static const struct pci_epc_features rockchip_pcie_epc_features = {

	.linkup_notifier = false,

	.msi_capable = true,
@@ -500,6 +512,7 @@ static const struct pci_epc_ops rockchip_pcie_epc_ops = { 
	.get_msi	= rockchip_pcie_ep_get_msi,

	.raise_irq	= rockchip_pcie_ep_raise_irq,

	.start		= rockchip_pcie_ep_start,

	.stop		= rockchip_pcie_ep_stop,

	.get_features	= rockchip_pcie_ep_get_features,

};

drivers/pci/controller/pcie-rockchip.h

+1 −0
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ 
#define   PCIE_CLIENT_CONF_ENABLE	  HIWORD_UPDATE_BIT(0x0001)

#define   PCIE_CLIENT_CONF_DISABLE       HIWORD_UPDATE(0x0001, 0)

#define   PCIE_CLIENT_LINK_TRAIN_ENABLE	  HIWORD_UPDATE_BIT(0x0002)

#define   PCIE_CLIENT_LINK_TRAIN_DISABLE  HIWORD_UPDATE(0x0002, 0)

#define   PCIE_CLIENT_ARI_ENABLE	  HIWORD_UPDATE_BIT(0x0008)

#define   PCIE_CLIENT_CONF_LANE_NUM(x)	  HIWORD_UPDATE(0x0030, ENCODE_LANES(x))

#define   PCIE_CLIENT_MODE_RC		  HIWORD_UPDATE_BIT(0x0040)