Commit 0011a51d authored by Tony Luck's avatar Tony Luck Committed by Dave Hansen
Browse files

perf/x86/lbr: Switch to new Intel CPU model defines 



New CPU #defines encode vendor and family as well as model.

Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
Signed-off-by: default avatarDave Hansen <dave.hansen@linux.intel.com>
Link: https://lore.kernel.org/all/20240424181500.41519-1-tony.luck%40intel.com
parent 5ee80094

arch/x86/events/intel/lbr.c

+2 −1
Original line number Diff line number Diff line
@@ -2,6 +2,7 @@ 
#include <linux/perf_event.h>

#include <linux/types.h>



#include <asm/cpu_device_id.h>

#include <asm/perf_event.h>

#include <asm/msr.h>
@@ -1457,7 +1458,7 @@ void __init intel_pmu_lbr_init_atom(void) 
	 * to have an operational LBR which can freeze

	 * on PMU interrupt

	 */

	if (boot_cpu_data.x86_model == 28

	if (boot_cpu_data.x86_vfm == INTEL_ATOM_BONNELL

	    && boot_cpu_data.x86_stepping < 10) {

		pr_cont("LBR disabled due to erratum");

		return;