Commit 005010f1 authored by Jouni Högander's avatar Jouni Högander
Browse files

drm/i915/psr: Split setting sff and cff bits away from intel_psr_force_update 



This is a clean-up and a preparation for adding own SFF and CFF registers
for LunarLake onwards.

Signed-off-by: default avatarJouni Högander <jouni.hogander@intel.com>
Reviewed-by: default avatarAnimesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250213064804.2077127-4-jouni.hogander@intel.com
parent 8e8cadfd

drivers/gpu/drm/i915/display/intel_psr.c

+31 −57
Original line number Diff line number Diff line
@@ -2327,15 +2327,6 @@ static u32 man_trk_ctl_continuos_full_frame(struct intel_display *display) 
static void intel_psr_force_update(struct intel_dp *intel_dp)

{

	struct intel_display *display = to_intel_display(intel_dp);

	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;



	if (intel_dp->psr.psr2_sel_fetch_enabled)

		intel_de_write(display,

			       PSR2_MAN_TRK_CTL(display, cpu_transcoder),

			       man_trk_ctl_enable_bit_get(display) |

			       man_trk_ctl_partial_frame_bit_get(display) |

			       man_trk_ctl_single_full_frame_bit_get(display) |

			       man_trk_ctl_continuos_full_frame(display));



	/*

	 * Display WA #0884: skl+
@@ -3131,31 +3122,31 @@ static void intel_psr_work(struct work_struct *work) 
	mutex_unlock(&intel_dp->psr.lock);

}



static void _psr_invalidate_handle(struct intel_dp *intel_dp)

static void intel_psr_configure_full_frame_update(struct intel_dp *intel_dp)

{

	struct intel_display *display = to_intel_display(intel_dp);

	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;



	if (intel_dp->psr.psr2_sel_fetch_enabled) {

		u32 val;



		if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {

			/* Send one update otherwise lag is observed in screen */

			intel_de_write(display,

				       CURSURFLIVE(display, intel_dp->psr.pipe),

				       0);

	if (!intel_dp->psr.psr2_sel_fetch_enabled)

		return;

		}



		val = man_trk_ctl_enable_bit_get(display) |

		      man_trk_ctl_partial_frame_bit_get(display) |

		      man_trk_ctl_continuos_full_frame(display);

	intel_de_write(display,

		       PSR2_MAN_TRK_CTL(display, cpu_transcoder),

			       val);

		intel_de_write(display,

			       CURSURFLIVE(display, intel_dp->psr.pipe), 0);

		       man_trk_ctl_enable_bit_get(display) |

		       man_trk_ctl_partial_frame_bit_get(display) |

		       man_trk_ctl_single_full_frame_bit_get(display) |

		       man_trk_ctl_continuos_full_frame(display));

}



static void _psr_invalidate_handle(struct intel_dp *intel_dp)

{

	if (intel_dp->psr.psr2_sel_fetch_enabled) {

		if (!intel_dp->psr.psr2_sel_fetch_cff_enabled) {

			intel_dp->psr.psr2_sel_fetch_cff_enabled = true;

			intel_psr_configure_full_frame_update(intel_dp);

		}



		intel_psr_force_update(intel_dp);

	} else {

		intel_psr_exit(intel_dp);

	}
@@ -3236,45 +3227,28 @@ static void _psr_flush_handle(struct intel_dp *intel_dp) 
{

	struct intel_display *display = to_intel_display(intel_dp);

	struct drm_i915_private *dev_priv = to_i915(display->drm);

	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;



	if (intel_dp->psr.psr2_sel_fetch_enabled) {

		if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {

			/* can we turn CFF off? */

			if (intel_dp->psr.busy_frontbuffer_bits == 0) {

				u32 val = man_trk_ctl_enable_bit_get(display) |

					man_trk_ctl_partial_frame_bit_get(display) |

					man_trk_ctl_single_full_frame_bit_get(display) |

					man_trk_ctl_continuos_full_frame(display);



				/*

				 * Set psr2_sel_fetch_cff_enabled as false to allow selective

				 * updates. Still keep cff bit enabled as we don't have proper

				 * SU configuration in case update is sent for any reason after

				 * sff bit gets cleared by the HW on next vblank.

				 */

				intel_de_write(display,

					       PSR2_MAN_TRK_CTL(display, cpu_transcoder),

					       val);

				intel_de_write(display,

					       CURSURFLIVE(display, intel_dp->psr.pipe),

					       0);

			if (intel_dp->psr.busy_frontbuffer_bits == 0)

				intel_dp->psr.psr2_sel_fetch_cff_enabled = false;

		}

		} else {



		/*

			 * continuous full frame is disabled, only a single full

			 * frame is required

		 * Still keep cff bit enabled as we don't have proper SU

		 * configuration in case update is sent for any reason after

		 * sff bit gets cleared by the HW on next vblank.

		 */

			intel_psr_force_update(intel_dp);

		intel_psr_configure_full_frame_update(intel_dp);

	}

	} else {



	intel_psr_force_update(intel_dp);



		if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits)

	if (!intel_dp->psr.psr2_sel_fetch_enabled && !intel_dp->psr.active &&

	    !intel_dp->psr.busy_frontbuffer_bits)

		queue_work(dev_priv->unordered_wq, &intel_dp->psr.work);

}

}



/**

 * intel_psr_flush - Flush PSR