Commit 0076a37a authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Daniel Lezcano
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dt-bindings: timer: renesas,tmu: Document input capture interrupt 



Some Timer Unit (TMU) instances with 3 channels support a fourth
interrupt: an input capture interrupt for the third channel.

While at it, document the meaning of the four interrupts, and add
"interrupt-names" for clarity.

Update the example to match reality.

Inspired by a patch by Yoshinori Sato for SH.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: default avatarDaniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/8cb38b5236213a467c6c0073f97ccc4bfd5a39ff.1706717378.git.geert+renesas@glider.be
parent 702107ed

Documentation/devicetree/bindings/timer/renesas,tmu.yaml

+16 −2
Original line number Diff line number Diff line
@@ -46,7 +46,19 @@ properties: 


  interrupts:

    minItems: 2

    maxItems: 3

    items:

      - description: Underflow interrupt, channel 0

      - description: Underflow interrupt, channel 1

      - description: Underflow interrupt, channel 2

      - description: Input capture interrupt, channel 2



  interrupt-names:

    minItems: 2

    items:

      - const: tuni0

      - const: tuni1

      - const: tuni2

      - const: ticpi2



  clocks:

    maxItems: 1
@@ -100,7 +112,9 @@ examples: 
            reg = <0xffd80000 0x30>;

            interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;

                         <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;

            interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";

            clocks = <&mstp0_clks R8A7779_CLK_TMU0>;

            clock-names = "fck";

            power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;