Commit 0092f62a authored by Ira Weiny's avatar Ira Weiny Committed by Dan Williams
Browse files

cxl/test: Add specific events 



Each type of event has different trace point outputs.

Add mock General Media Event, DRAM event, and Memory Module Event
records to the mock list of events returned.

Reviewed-by: default avatarDan Williams <dan.j.williams@intel.com>
Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: default avatarIra Weiny <ira.weiny@intel.com>
Link: https://lore.kernel.org/r/20221216-cxl-ev-log-v7-7-2316a5c8f7d8@intel.com


Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent d1dca858

tools/testing/cxl/test/mem.c

+73 −0
Original line number Diff line number Diff line
@@ -277,12 +277,85 @@ struct cxl_event_record_raw hardware_replace = { 
	.data = { 0xDE, 0xAD, 0xBE, 0xEF },

};



struct cxl_event_gen_media gen_media = {

	.hdr = {

		.id = UUID_INIT(0xfbcd0a77, 0xc260, 0x417f,

				0x85, 0xa9, 0x08, 0x8b, 0x16, 0x21, 0xeb, 0xa6),

		.length = sizeof(struct cxl_event_gen_media),

		.flags[0] = CXL_EVENT_RECORD_FLAG_PERMANENT,

		/* .handle = Set dynamically */

		.related_handle = cpu_to_le16(0),

	},

	.phys_addr = cpu_to_le64(0x2000),

	.descriptor = CXL_GMER_EVT_DESC_UNCORECTABLE_EVENT,

	.type = CXL_GMER_MEM_EVT_TYPE_DATA_PATH_ERROR,

	.transaction_type = CXL_GMER_TRANS_HOST_WRITE,

	/* .validity_flags = <set below> */

	.channel = 1,

	.rank = 30

};



struct cxl_event_dram dram = {

	.hdr = {

		.id = UUID_INIT(0x601dcbb3, 0x9c06, 0x4eab,

				0xb8, 0xaf, 0x4e, 0x9b, 0xfb, 0x5c, 0x96, 0x24),

		.length = sizeof(struct cxl_event_dram),

		.flags[0] = CXL_EVENT_RECORD_FLAG_PERF_DEGRADED,

		/* .handle = Set dynamically */

		.related_handle = cpu_to_le16(0),

	},

	.phys_addr = cpu_to_le64(0x8000),

	.descriptor = CXL_GMER_EVT_DESC_THRESHOLD_EVENT,

	.type = CXL_GMER_MEM_EVT_TYPE_INV_ADDR,

	.transaction_type = CXL_GMER_TRANS_INTERNAL_MEDIA_SCRUB,

	/* .validity_flags = <set below> */

	.channel = 1,

	.bank_group = 5,

	.bank = 2,

	.column = {0xDE, 0xAD},

};



struct cxl_event_mem_module mem_module = {

	.hdr = {

		.id = UUID_INIT(0xfe927475, 0xdd59, 0x4339,

				0xa5, 0x86, 0x79, 0xba, 0xb1, 0x13, 0xb7, 0x74),

		.length = sizeof(struct cxl_event_mem_module),

		/* .handle = Set dynamically */

		.related_handle = cpu_to_le16(0),

	},

	.event_type = CXL_MMER_TEMP_CHANGE,

	.info = {

		.health_status = CXL_DHI_HS_PERFORMANCE_DEGRADED,

		.media_status = CXL_DHI_MS_ALL_DATA_LOST,

		.add_status = (CXL_DHI_AS_CRITICAL << 2) |

			      (CXL_DHI_AS_WARNING << 4) |

			      (CXL_DHI_AS_WARNING << 5),

		.device_temp = { 0xDE, 0xAD},

		.dirty_shutdown_cnt = { 0xde, 0xad, 0xbe, 0xef },

		.cor_vol_err_cnt = { 0xde, 0xad, 0xbe, 0xef },

		.cor_per_err_cnt = { 0xde, 0xad, 0xbe, 0xef },

	}

};



static void cxl_mock_add_event_logs(struct mock_event_store *mes)

{

	put_unaligned_le16(CXL_GMER_VALID_CHANNEL | CXL_GMER_VALID_RANK,

			   &gen_media.validity_flags);



	put_unaligned_le16(CXL_DER_VALID_CHANNEL | CXL_DER_VALID_BANK_GROUP |

			   CXL_DER_VALID_BANK | CXL_DER_VALID_COLUMN,

			   &dram.validity_flags);



	mes_add_event(mes, CXL_EVENT_TYPE_INFO, &maint_needed);

	mes_add_event(mes, CXL_EVENT_TYPE_INFO,

		      (struct cxl_event_record_raw *)&gen_media);

	mes_add_event(mes, CXL_EVENT_TYPE_INFO,

		      (struct cxl_event_record_raw *)&mem_module);

	mes->ev_status |= CXLDEV_EVENT_STATUS_INFO;



	mes_add_event(mes, CXL_EVENT_TYPE_FATAL, &hardware_replace);

	mes_add_event(mes, CXL_EVENT_TYPE_FATAL,

		      (struct cxl_event_record_raw *)&dram);

	mes->ev_status |= CXLDEV_EVENT_STATUS_FATAL;

}