Commit 00a76783 authored by Lorenzo Bianconi's avatar Lorenzo Bianconi Committed by Paolo Abeni
Browse files

net: airoha: Introduce flowtable offload support 



Introduce netfilter flowtable integration in order to allow airoha_eth
driver to offload 5-tuple flower rules learned by the PPE module if the
user accelerates them using a nft configuration similar to the one reported
below:

table inet filter {
	flowtable ft {
		hook ingress priority filter
		devices = { lan1, lan2, lan3, lan4, eth1 }
		flags offload;
	}
	chain forward {
		type filter hook forward priority filter; policy accept;
		meta l4proto { tcp, udp } flow add @ft
	}
}

Tested-by: default avatarSayantan Nandy <sayantan.nandy@airoha.com>
Signed-off-by: default avatarLorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parent 23290c7b

drivers/net/ethernet/airoha/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -3,5 +3,6 @@ 
# Airoha for the Mediatek SoCs built-in ethernet macs

#



obj-$(CONFIG_NET_AIROHA) += airoha_eth.o

obj-$(CONFIG_NET_AIROHA) += airoha-eth.o

airoha-eth-y := airoha_eth.o airoha_ppe.o

obj-$(CONFIG_NET_AIROHA_NPU) += airoha_npu.o

drivers/net/ethernet/airoha/airoha_eth.c

+59 −1
Original line number Diff line number Diff line
@@ -8,7 +8,6 @@ 
#include <linux/platform_device.h>

#include <linux/tcp.h>

#include <linux/u64_stats_sync.h>

#include <net/dsa.h>

#include <net/dst_metadata.h>

#include <net/page_pool/helpers.h>

#include <net/pkt_cls.h>
@@ -619,6 +618,7 @@ static int airoha_qdma_rx_process(struct airoha_queue *q, int budget) 
	while (done < budget) {

		struct airoha_queue_entry *e = &q->entry[q->tail];

		struct airoha_qdma_desc *desc = &q->desc[q->tail];

		u32 hash, reason, msg1 = le32_to_cpu(desc->msg1);

		dma_addr_t dma_addr = le32_to_cpu(desc->addr);

		u32 desc_ctrl = le32_to_cpu(desc->ctrl);

		struct airoha_gdm_port *port;
@@ -681,6 +681,15 @@ static int airoha_qdma_rx_process(struct airoha_queue *q, int budget) 
						  &port->dsa_meta[sptag]->dst);

		}



		hash = FIELD_GET(AIROHA_RXD4_FOE_ENTRY, msg1);

		if (hash != AIROHA_RXD4_FOE_ENTRY)

			skb_set_hash(skb, jhash_1word(hash, 0),

				     PKT_HASH_TYPE_L4);



		reason = FIELD_GET(AIROHA_RXD4_PPE_CPU_REASON, msg1);

		if (reason == PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED)

			airoha_ppe_check_skb(eth->ppe, hash);



		napi_gro_receive(&q->napi, skb);



		done++;
@@ -1301,6 +1310,10 @@ static int airoha_hw_init(struct platform_device *pdev, 
			return err;

	}



	err = airoha_ppe_init(eth);

	if (err)

		return err;



	set_bit(DEV_STATE_INITIALIZED, &eth->state);



	return 0;
@@ -2168,6 +2181,47 @@ static int airoha_tc_htb_alloc_leaf_queue(struct airoha_gdm_port *port, 
	return 0;

}



static int airoha_dev_setup_tc_block(struct airoha_gdm_port *port,

				     struct flow_block_offload *f)

{

	flow_setup_cb_t *cb = airoha_ppe_setup_tc_block_cb;

	static LIST_HEAD(block_cb_list);

	struct flow_block_cb *block_cb;



	if (f->binder_type != FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS)

		return -EOPNOTSUPP;



	f->driver_block_list = &block_cb_list;

	switch (f->command) {

	case FLOW_BLOCK_BIND:

		block_cb = flow_block_cb_lookup(f->block, cb, port->dev);

		if (block_cb) {

			flow_block_cb_incref(block_cb);

			return 0;

		}

		block_cb = flow_block_cb_alloc(cb, port->dev, port->dev, NULL);

		if (IS_ERR(block_cb))

			return PTR_ERR(block_cb);



		flow_block_cb_incref(block_cb);

		flow_block_cb_add(block_cb, f);

		list_add_tail(&block_cb->driver_list, &block_cb_list);

		return 0;

	case FLOW_BLOCK_UNBIND:

		block_cb = flow_block_cb_lookup(f->block, cb, port->dev);

		if (!block_cb)

			return -ENOENT;



		if (!flow_block_cb_decref(block_cb)) {

			flow_block_cb_remove(block_cb, f);

			list_del(&block_cb->driver_list);

		}

		return 0;

	default:

		return -EOPNOTSUPP;

	}

}



static void airoha_tc_remove_htb_queue(struct airoha_gdm_port *port, int queue)

{

	struct net_device *dev = port->dev;
@@ -2251,6 +2305,9 @@ static int airoha_dev_tc_setup(struct net_device *dev, enum tc_setup_type type, 
		return airoha_tc_setup_qdisc_ets(port, type_data);

	case TC_SETUP_QDISC_HTB:

		return airoha_tc_setup_qdisc_htb(port, type_data);

	case TC_SETUP_BLOCK:

	case TC_SETUP_FT:

		return airoha_dev_setup_tc_block(port, type_data);

	default:

		return -EOPNOTSUPP;

	}
@@ -2507,6 +2564,7 @@ static void airoha_remove(struct platform_device *pdev) 
	}

	free_netdev(eth->napi_dev);



	airoha_ppe_deinit(eth);

	platform_set_drvdata(pdev, NULL);

}

drivers/net/ethernet/airoha/airoha_eth.h

+250 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
#include <linux/kernel.h>

#include <linux/netdevice.h>

#include <linux/reset.h>

#include <net/dsa.h>



#define AIROHA_MAX_NUM_GDM_PORTS	4

#define AIROHA_MAX_NUM_QDMA		2
@@ -44,6 +45,15 @@ 
#define QDMA_METER_IDX(_n)		((_n) & 0xff)

#define QDMA_METER_GROUP(_n)		(((_n) >> 8) & 0x3)



#define PPE_NUM				2

#define PPE1_SRAM_NUM_ENTRIES		(8 * 1024)

#define PPE_SRAM_NUM_ENTRIES		(2 * PPE1_SRAM_NUM_ENTRIES)

#define PPE_DRAM_NUM_ENTRIES		(16 * 1024)

#define PPE_NUM_ENTRIES			(PPE_SRAM_NUM_ENTRIES + PPE_DRAM_NUM_ENTRIES)

#define PPE_HASH_MASK			(PPE_NUM_ENTRIES - 1)

#define PPE_ENTRY_SIZE			80

#define PPE_RAM_NUM_ENTRIES_SHIFT(_n)	(__ffs((_n) >> 10))



#define MTK_HDR_LEN			4

#define MTK_HDR_XMIT_TAGGED_TPID_8100	1

#define MTK_HDR_XMIT_TAGGED_TPID_88A8	2
@@ -195,6 +205,224 @@ struct airoha_hw_stats { 
	u64 rx_len[7];

};



enum {

	PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED = 0x0f,

};



enum {

	AIROHA_FOE_STATE_INVALID,

	AIROHA_FOE_STATE_UNBIND,

	AIROHA_FOE_STATE_BIND,

	AIROHA_FOE_STATE_FIN

};



enum {

	PPE_PKT_TYPE_IPV4_HNAPT = 0,

	PPE_PKT_TYPE_IPV4_ROUTE = 1,

	PPE_PKT_TYPE_BRIDGE = 2,

	PPE_PKT_TYPE_IPV4_DSLITE = 3,

	PPE_PKT_TYPE_IPV6_ROUTE_3T = 4,

	PPE_PKT_TYPE_IPV6_ROUTE_5T = 5,

	PPE_PKT_TYPE_IPV6_6RD = 7,

};



#define AIROHA_FOE_MAC_SMAC_ID		GENMASK(20, 16)

#define AIROHA_FOE_MAC_PPPOE_ID		GENMASK(15, 0)



struct airoha_foe_mac_info_common {

	u16 vlan1;

	u16 etype;



	u32 dest_mac_hi;



	u16 vlan2;

	u16 dest_mac_lo;



	u32 src_mac_hi;

};



struct airoha_foe_mac_info {

	struct airoha_foe_mac_info_common common;



	u16 pppoe_id;

	u16 src_mac_lo;

};



#define AIROHA_FOE_IB1_UNBIND_PREBIND		BIT(24)

#define AIROHA_FOE_IB1_UNBIND_PACKETS		GENMASK(23, 8)

#define AIROHA_FOE_IB1_UNBIND_TIMESTAMP		GENMASK(7, 0)



#define AIROHA_FOE_IB1_BIND_STATIC		BIT(31)

#define AIROHA_FOE_IB1_BIND_UDP			BIT(30)

#define AIROHA_FOE_IB1_BIND_STATE		GENMASK(29, 28)

#define AIROHA_FOE_IB1_BIND_PACKET_TYPE		GENMASK(27, 25)

#define AIROHA_FOE_IB1_BIND_TTL			BIT(24)

#define AIROHA_FOE_IB1_BIND_TUNNEL_DECAP	BIT(23)

#define AIROHA_FOE_IB1_BIND_PPPOE		BIT(22)

#define AIROHA_FOE_IB1_BIND_VPM			GENMASK(21, 20)

#define AIROHA_FOE_IB1_BIND_VLAN_LAYER		GENMASK(19, 16)

#define AIROHA_FOE_IB1_BIND_KEEPALIVE		BIT(15)

#define AIROHA_FOE_IB1_BIND_TIMESTAMP		GENMASK(14, 0)



#define AIROHA_FOE_IB2_DSCP			GENMASK(31, 24)

#define AIROHA_FOE_IB2_PORT_AG			GENMASK(23, 13)

#define AIROHA_FOE_IB2_PCP			BIT(12)

#define AIROHA_FOE_IB2_MULTICAST		BIT(11)

#define AIROHA_FOE_IB2_FAST_PATH		BIT(10)

#define AIROHA_FOE_IB2_PSE_QOS			BIT(9)

#define AIROHA_FOE_IB2_PSE_PORT			GENMASK(8, 5)

#define AIROHA_FOE_IB2_NBQ			GENMASK(4, 0)



#define AIROHA_FOE_ACTDP			GENMASK(31, 24)

#define AIROHA_FOE_SHAPER_ID			GENMASK(23, 16)

#define AIROHA_FOE_CHANNEL			GENMASK(15, 11)

#define AIROHA_FOE_QID				GENMASK(10, 8)

#define AIROHA_FOE_DPI				BIT(7)

#define AIROHA_FOE_TUNNEL			BIT(6)

#define AIROHA_FOE_TUNNEL_ID			GENMASK(5, 0)



struct airoha_foe_bridge {

	u32 dest_mac_hi;



	u16 src_mac_hi;

	u16 dest_mac_lo;



	u32 src_mac_lo;



	u32 ib2;



	u32 rsv[5];



	u32 data;



	struct airoha_foe_mac_info l2;

};



struct airoha_foe_ipv4_tuple {

	u32 src_ip;

	u32 dest_ip;

	union {

		struct {

			u16 dest_port;

			u16 src_port;

		};

		struct {

			u8 protocol;

			u8 _pad[3]; /* fill with 0xa5a5a5 */

		};

		u32 ports;

	};

};



struct airoha_foe_ipv4 {

	struct airoha_foe_ipv4_tuple orig_tuple;



	u32 ib2;



	struct airoha_foe_ipv4_tuple new_tuple;



	u32 rsv[2];



	u32 data;



	struct airoha_foe_mac_info l2;

};



struct airoha_foe_ipv4_dslite {

	struct airoha_foe_ipv4_tuple ip4;



	u32 ib2;



	u8 flow_label[3];

	u8 priority;



	u32 rsv[4];



	u32 data;



	struct airoha_foe_mac_info l2;

};



struct airoha_foe_ipv6 {

	u32 src_ip[4];

	u32 dest_ip[4];



	union {

		struct {

			u16 dest_port;

			u16 src_port;

		};

		struct {

			u8 protocol;

			u8 pad[3];

		};

		u32 ports;

	};



	u32 data;



	u32 ib2;



	struct airoha_foe_mac_info_common l2;

};



struct airoha_foe_entry {

	union {

		struct {

			u32 ib1;

			union {

				struct airoha_foe_bridge bridge;

				struct airoha_foe_ipv4 ipv4;

				struct airoha_foe_ipv4_dslite dslite;

				struct airoha_foe_ipv6 ipv6;

				DECLARE_FLEX_ARRAY(u32, d);

			};

		};

		u8 data[PPE_ENTRY_SIZE];

	};

};



struct airoha_flow_data {

	struct ethhdr eth;



	union {

		struct {

			__be32 src_addr;

			__be32 dst_addr;

		} v4;



		struct {

			struct in6_addr src_addr;

			struct in6_addr dst_addr;

		} v6;

	};



	__be16 src_port;

	__be16 dst_port;



	struct {

		struct {

			u16 id;

			__be16 proto;

		} hdr[2];

		u8 num;

	} vlan;

	struct {

		u16 sid;

		u8 num;

	} pppoe;

};



struct airoha_flow_table_entry {

	struct hlist_node list;



	struct airoha_foe_entry data;

	u32 hash;



	struct rhash_head node;

	unsigned long cookie;

};



struct airoha_qdma {

	struct airoha_eth *eth;

	void __iomem *regs;
@@ -234,6 +462,19 @@ struct airoha_gdm_port { 
	struct metadata_dst *dsa_meta[AIROHA_MAX_DSA_PORTS];

};



#define AIROHA_RXD4_PPE_CPU_REASON	GENMASK(20, 16)

#define AIROHA_RXD4_FOE_ENTRY		GENMASK(15, 0)



struct airoha_ppe {

	struct airoha_eth *eth;



	void *foe;

	dma_addr_t foe_dma;



	struct hlist_head *foe_flow;

	u16 foe_check_time[PPE_NUM_ENTRIES];

};



struct airoha_eth {

	struct device *dev;
@@ -242,6 +483,9 @@ struct airoha_eth { 


	struct airoha_npu __rcu *npu;



	struct airoha_ppe *ppe;

	struct rhashtable flow_table;



	struct reset_control_bulk_data rsts[AIROHA_MAX_NUM_RSTS];

	struct reset_control_bulk_data xsi_rsts[AIROHA_MAX_NUM_XSI_RSTS];
@@ -277,4 +521,10 @@ u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val); 
#define airoha_qdma_clear(qdma, offset, val)			\

	airoha_rmw((qdma)->regs, (offset), (val), 0)



void airoha_ppe_check_skb(struct airoha_ppe *ppe, u16 hash);

int airoha_ppe_setup_tc_block_cb(enum tc_setup_type type, void *type_data,

				 void *cb_priv);

int airoha_ppe_init(struct airoha_eth *eth);

void airoha_ppe_deinit(struct airoha_eth *eth);



#endif /* AIROHA_ETH_H */

drivers/net/ethernet/airoha/airoha_ppe.c

0 → 100644
+901 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/airoha/airoha_regs.h

+102 −5
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#define CDM1_BASE			0x0400

#define GDM1_BASE			0x0500

#define PPE1_BASE			0x0c00

#define PPE2_BASE			0x1c00



#define CDM2_BASE			0x1400

#define GDM2_BASE			0x1500
@@ -36,6 +37,7 @@ 
#define FE_RST_GDM3_MBI_ARB_MASK	BIT(2)

#define FE_RST_CORE_MASK		BIT(0)



#define REG_FE_FOE_TS			0x0010

#define REG_FE_WAN_MAC_H		0x0030

#define REG_FE_LAN_MAC_H		0x0040
@@ -192,11 +194,106 @@ 
#define REG_FE_GDM_RX_ETH_L511_CNT_L(_n)	(GDM_BASE(_n) + 0x198)

#define REG_FE_GDM_RX_ETH_L1023_CNT_L(_n)	(GDM_BASE(_n) + 0x19c)



#define REG_PPE1_TB_HASH_CFG		(PPE1_BASE + 0x250)

#define PPE1_SRAM_TABLE_EN_MASK		BIT(0)

#define PPE1_SRAM_HASH1_EN_MASK		BIT(8)

#define PPE1_DRAM_TABLE_EN_MASK		BIT(16)

#define PPE1_DRAM_HASH1_EN_MASK		BIT(24)

#define REG_PPE_GLO_CFG(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x200)

#define PPE_GLO_CFG_BUSY_MASK			BIT(31)

#define PPE_GLO_CFG_FLOW_DROP_UPDATE_MASK	BIT(9)

#define PPE_GLO_CFG_PSE_HASH_OFS_MASK		BIT(6)

#define PPE_GLO_CFG_PPE_BSWAP_MASK		BIT(5)

#define PPE_GLO_CFG_TTL_DROP_MASK		BIT(4)

#define PPE_GLO_CFG_IP4_CS_DROP_MASK		BIT(3)

#define PPE_GLO_CFG_IP4_L4_CS_DROP_MASK		BIT(2)

#define PPE_GLO_CFG_EN_MASK			BIT(0)



#define REG_PPE_PPE_FLOW_CFG(_n)		(((_n) ? PPE2_BASE : PPE1_BASE) + 0x204)

#define PPE_FLOW_CFG_IP6_HASH_GRE_KEY_MASK	BIT(20)

#define PPE_FLOW_CFG_IP4_HASH_GRE_KEY_MASK	BIT(19)

#define PPE_FLOW_CFG_IP4_HASH_FLOW_LABEL_MASK	BIT(18)

#define PPE_FLOW_CFG_IP4_NAT_FRAG_MASK		BIT(17)

#define PPE_FLOW_CFG_IP_PROTO_BLACKLIST_MASK	BIT(16)

#define PPE_FLOW_CFG_IP4_DSLITE_MASK		BIT(14)

#define PPE_FLOW_CFG_IP4_NAPT_MASK		BIT(13)

#define PPE_FLOW_CFG_IP4_NAT_MASK		BIT(12)

#define PPE_FLOW_CFG_IP6_6RD_MASK		BIT(10)

#define PPE_FLOW_CFG_IP6_5T_ROUTE_MASK		BIT(9)

#define PPE_FLOW_CFG_IP6_3T_ROUTE_MASK		BIT(8)

#define PPE_FLOW_CFG_IP4_UDP_FRAG_MASK		BIT(7)

#define PPE_FLOW_CFG_IP4_TCP_FRAG_MASK		BIT(6)



#define REG_PPE_IP_PROTO_CHK(_n)		(((_n) ? PPE2_BASE : PPE1_BASE) + 0x208)

#define PPE_IP_PROTO_CHK_IPV4_MASK		GENMASK(15, 0)

#define PPE_IP_PROTO_CHK_IPV6_MASK		GENMASK(31, 16)



#define REG_PPE_TB_CFG(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x21c)

#define PPE_SRAM_TB_NUM_ENTRY_MASK		GENMASK(26, 24)

#define PPE_TB_CFG_KEEPALIVE_MASK		GENMASK(13, 12)

#define PPE_TB_CFG_AGE_TCP_FIN_MASK		BIT(11)

#define PPE_TB_CFG_AGE_UDP_MASK			BIT(10)

#define PPE_TB_CFG_AGE_TCP_MASK			BIT(9)

#define PPE_TB_CFG_AGE_UNBIND_MASK		BIT(8)

#define PPE_TB_CFG_AGE_NON_L4_MASK		BIT(7)

#define PPE_TB_CFG_AGE_PREBIND_MASK		BIT(6)

#define PPE_TB_CFG_SEARCH_MISS_MASK		GENMASK(5, 4)

#define PPE_TB_ENTRY_SIZE_MASK			BIT(3)

#define PPE_DRAM_TB_NUM_ENTRY_MASK		GENMASK(2, 0)



#define REG_PPE_TB_BASE(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x220)



#define REG_PPE_BIND_RATE(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x228)

#define PPE_BIND_RATE_L2B_BIND_MASK		GENMASK(31, 16)

#define PPE_BIND_RATE_BIND_MASK			GENMASK(15, 0)



#define REG_PPE_BIND_LIMIT0(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x22c)

#define PPE_BIND_LIMIT0_HALF_MASK		GENMASK(29, 16)

#define PPE_BIND_LIMIT0_QUARTER_MASK		GENMASK(13, 0)



#define REG_PPE_BIND_LIMIT1(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x230)

#define PPE_BIND_LIMIT1_NON_L4_MASK		GENMASK(23, 16)

#define PPE_BIND_LIMIT1_FULL_MASK		GENMASK(13, 0)



#define REG_PPE_BND_AGE0(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x23c)

#define PPE_BIND_AGE0_DELTA_NON_L4		GENMASK(30, 16)

#define PPE_BIND_AGE0_DELTA_UDP			GENMASK(14, 0)



#define REG_PPE_UNBIND_AGE(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x238)

#define PPE_UNBIND_AGE_MIN_PACKETS_MASK		GENMASK(31, 16)

#define PPE_UNBIND_AGE_DELTA_MASK		GENMASK(7, 0)



#define REG_PPE_BND_AGE1(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x240)

#define PPE_BIND_AGE1_DELTA_TCP_FIN		GENMASK(30, 16)

#define PPE_BIND_AGE1_DELTA_TCP			GENMASK(14, 0)



#define REG_PPE_HASH_SEED(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x244)

#define PPE_HASH_SEED				0x12345678



#define REG_PPE_DFT_CPORT0(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x248)



#define REG_PPE_DFT_CPORT1(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x24c)



#define REG_PPE_TB_HASH_CFG(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x250)

#define PPE_DRAM_HASH1_MODE_MASK		GENMASK(31, 28)

#define PPE_DRAM_HASH1_EN_MASK			BIT(24)

#define PPE_DRAM_HASH0_MODE_MASK		GENMASK(23, 20)

#define PPE_DRAM_TABLE_EN_MASK			BIT(16)

#define PPE_SRAM_HASH1_MODE_MASK		GENMASK(15, 12)

#define PPE_SRAM_HASH1_EN_MASK			BIT(8)

#define PPE_SRAM_HASH0_MODE_MASK		GENMASK(7, 4)

#define PPE_SRAM_TABLE_EN_MASK			BIT(0)



#define REG_PPE_MTU_BASE(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x304)

#define REG_PPE_MTU(_m, _n)			(REG_PPE_MTU_BASE(_m) + ((_n) << 2))

#define FP1_EGRESS_MTU_MASK			GENMASK(29, 16)

#define FP0_EGRESS_MTU_MASK			GENMASK(13, 0)



#define REG_PPE_RAM_CTRL(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x31c)

#define PPE_SRAM_CTRL_ACK_MASK			BIT(31)

#define PPE_SRAM_CTRL_DUAL_SUCESS_MASK		BIT(30)

#define PPE_SRAM_CTRL_ENTRY_MASK		GENMASK(23, 8)

#define PPE_SRAM_WR_DUAL_DIRECTION_MASK		BIT(2)

#define PPE_SRAM_CTRL_WR_MASK			BIT(1)

#define PPE_SRAM_CTRL_REQ_MASK			BIT(0)



#define REG_PPE_RAM_BASE(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x320)

#define REG_PPE_RAM_ENTRY(_m, _n)		(REG_PPE_RAM_BASE(_m) + ((_n) << 2))



#define REG_FE_GDM_TX_OK_PKT_CNT_H(_n)		(GDM_BASE(_n) + 0x280)

#define REG_FE_GDM_TX_OK_BYTE_CNT_H(_n)		(GDM_BASE(_n) + 0x284)