Commit 00cace8b authored by Dr. David Alan Gilbert's avatar Dr. David Alan Gilbert Committed by Alex Deucher
Browse files

drm/amd/display: Remove unused dcn_find_dcfclk_suits_all 



dcn_find_dcfclk_suits_all() last use was removed by 2018's
commit 4fd994c4 ("drm/amd/display: Start using the new pp_smu
interface")

Remove it, and the dcn_find_normalized_clock_vdd_Level helper it used.

Signed-off-by: default avatarDr. David Alan Gilbert <linux@treblig.org>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 21615ea4

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

+0 −132
Original line number Diff line number Diff line
@@ -1312,138 +1312,6 @@ bool dcn_validate_bandwidth( 
		return false;

}



static unsigned int dcn_find_normalized_clock_vdd_Level(

	const struct dc *dc,

	enum dm_pp_clock_type clocks_type,

	int clocks_in_khz)

{

	int vdd_level = dcn_bw_v_min0p65;



	if (clocks_in_khz == 0)/*todo some clock not in the considerations*/

		return vdd_level;



	switch (clocks_type) {

	case DM_PP_CLOCK_TYPE_DISPLAY_CLK:

		if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmax0p9*1000) {

			vdd_level = dcn_bw_v_max0p91;

			BREAK_TO_DEBUGGER();

		} else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vnom0p8*1000) {

			vdd_level = dcn_bw_v_max0p9;

		} else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmid0p72*1000) {

			vdd_level = dcn_bw_v_nom0p8;

		} else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmin0p65*1000) {

			vdd_level = dcn_bw_v_mid0p72;

		} else

			vdd_level = dcn_bw_v_min0p65;

		break;

	case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:

		if (clocks_in_khz > dc->dcn_soc->phyclkv_max0p9*1000) {

			vdd_level = dcn_bw_v_max0p91;

			BREAK_TO_DEBUGGER();

		} else if (clocks_in_khz > dc->dcn_soc->phyclkv_nom0p8*1000) {

			vdd_level = dcn_bw_v_max0p9;

		} else if (clocks_in_khz > dc->dcn_soc->phyclkv_mid0p72*1000) {

			vdd_level = dcn_bw_v_nom0p8;

		} else if (clocks_in_khz > dc->dcn_soc->phyclkv_min0p65*1000) {

			vdd_level = dcn_bw_v_mid0p72;

		} else

			vdd_level = dcn_bw_v_min0p65;

		break;



	case DM_PP_CLOCK_TYPE_DPPCLK:

		if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmax0p9*1000) {

			vdd_level = dcn_bw_v_max0p91;

			BREAK_TO_DEBUGGER();

		} else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vnom0p8*1000) {

			vdd_level = dcn_bw_v_max0p9;

		} else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmid0p72*1000) {

			vdd_level = dcn_bw_v_nom0p8;

		} else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmin0p65*1000) {

			vdd_level = dcn_bw_v_mid0p72;

		} else

			vdd_level = dcn_bw_v_min0p65;

		break;



	case DM_PP_CLOCK_TYPE_MEMORY_CLK:

		{

			unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc->number_of_channels);



			if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9*1000000/factor) {

				vdd_level = dcn_bw_v_max0p91;

				BREAK_TO_DEBUGGER();

			} else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8*1000000/factor) {

				vdd_level = dcn_bw_v_max0p9;

			} else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72*1000000/factor) {

				vdd_level = dcn_bw_v_nom0p8;

			} else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65*1000000/factor) {

				vdd_level = dcn_bw_v_mid0p72;

			} else

				vdd_level = dcn_bw_v_min0p65;

		}

		break;



	case DM_PP_CLOCK_TYPE_DCFCLK:

		if (clocks_in_khz > dc->dcn_soc->dcfclkv_max0p9*1000) {

			vdd_level = dcn_bw_v_max0p91;

			BREAK_TO_DEBUGGER();

		} else if (clocks_in_khz > dc->dcn_soc->dcfclkv_nom0p8*1000) {

			vdd_level = dcn_bw_v_max0p9;

		} else if (clocks_in_khz > dc->dcn_soc->dcfclkv_mid0p72*1000) {

			vdd_level = dcn_bw_v_nom0p8;

		} else if (clocks_in_khz > dc->dcn_soc->dcfclkv_min0p65*1000) {

			vdd_level = dcn_bw_v_mid0p72;

		} else

			vdd_level = dcn_bw_v_min0p65;

		break;



	default:

		 break;

	}

	return vdd_level;

}



unsigned int dcn_find_dcfclk_suits_all(

	const struct dc *dc,

	struct dc_clocks *clocks)

{

	unsigned vdd_level, vdd_level_temp;

	unsigned dcf_clk;



	/*find a common supported voltage level*/

	vdd_level = dcn_find_normalized_clock_vdd_Level(

		dc, DM_PP_CLOCK_TYPE_DISPLAY_CLK, clocks->dispclk_khz);

	vdd_level_temp = dcn_find_normalized_clock_vdd_Level(

		dc, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, clocks->phyclk_khz);



	vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);

	vdd_level_temp = dcn_find_normalized_clock_vdd_Level(

		dc, DM_PP_CLOCK_TYPE_DPPCLK, clocks->dppclk_khz);

	vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);



	vdd_level_temp = dcn_find_normalized_clock_vdd_Level(

		dc, DM_PP_CLOCK_TYPE_MEMORY_CLK, clocks->fclk_khz);

	vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);

	vdd_level_temp = dcn_find_normalized_clock_vdd_Level(

		dc, DM_PP_CLOCK_TYPE_DCFCLK, clocks->dcfclk_khz);



	/*find that level conresponding dcfclk*/

	vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);

	if (vdd_level == dcn_bw_v_max0p91) {

		BREAK_TO_DEBUGGER();

		dcf_clk = dc->dcn_soc->dcfclkv_max0p9*1000;

	} else if (vdd_level == dcn_bw_v_max0p9)

		dcf_clk =  dc->dcn_soc->dcfclkv_max0p9*1000;

	else if (vdd_level == dcn_bw_v_nom0p8)

		dcf_clk =  dc->dcn_soc->dcfclkv_nom0p8*1000;

	else if (vdd_level == dcn_bw_v_mid0p72)

		dcf_clk =  dc->dcn_soc->dcfclkv_mid0p72*1000;

	else

		dcf_clk =  dc->dcn_soc->dcfclkv_min0p65*1000;



	DC_LOG_BANDWIDTH_CALCS("\tdcf_clk for voltage = %d\n", dcf_clk);

	return dcf_clk;

}



void dcn_bw_update_from_pplib_fclks(

	struct dc *dc,

	struct dm_pp_clock_levels_with_voltage *fclks)

drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h

+0 −4
Original line number Diff line number Diff line
@@ -624,10 +624,6 @@ bool dcn_validate_bandwidth( 
		struct dc_state *context,

		bool fast_validate);



unsigned int dcn_find_dcfclk_suits_all(

	const struct dc *dc,

	struct dc_clocks *clocks);



void dcn_get_soc_clks(

		struct dc *dc,

		int *min_fclk_khz,