Commit 014b839f authored by Chen Wang's avatar Chen Wang
Browse files

riscv: sophgo: dts: add mmc controllers for SG2042 SoC 



SG2042 has two MMC controller, one for emmc, another for sd-card.

Signed-off-by: default avatarChen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/03ac9ec9c23bbe4c3b30271e76537bdbe5638665.1722847198.git.unicorn_wang@outlook.com


Signed-off-by: default avatarInochi Amaoto <inochiama@outlook.com>
parent c8eb04ae

arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts

+17 −0
Original line number Diff line number Diff line
@@ -26,6 +26,23 @@ &cgi_dpll1 { 
	clock-frequency = <25000000>;

};



&emmc {

	bus-width = <4>;

	no-sdio;

	no-sd;

	non-removable;

	wp-inverted;

	status = "okay";

};



&sd {

	bus-width = <4>;

	no-sdio;

	no-mmc;

	wp-inverted;

	status = "okay";

};



&uart0 {

	status = "okay";

};

arch/riscv/boot/dts/sophgo/sg2042.dtsi

+28 −0
Original line number Diff line number Diff line
@@ -451,5 +451,33 @@ uart0: serial@7040000000 { 
			resets = <&rstgen RST_UART0>;

			status = "disabled";

		};



		emmc: mmc@704002a000 {

			compatible = "sophgo,sg2042-dwcmshc";

			reg = <0x70 0x4002a000 0x0 0x1000>;

			interrupt-parent = <&intc>;

			interrupts = <134 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clkgen GATE_CLK_EMMC_100M>,

				 <&clkgen GATE_CLK_AXI_EMMC>,

				 <&clkgen GATE_CLK_100K_EMMC>;

			clock-names = "core",

				      "bus",

				      "timer";

			status = "disabled";

		};



		sd: mmc@704002b000 {

			compatible = "sophgo,sg2042-dwcmshc";

			reg = <0x70 0x4002b000 0x0 0x1000>;

			interrupt-parent = <&intc>;

			interrupts = <136 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clkgen GATE_CLK_SD_100M>,

				 <&clkgen GATE_CLK_AXI_SD>,

				 <&clkgen GATE_CLK_100K_SD>;

			clock-names = "core",

				      "bus",

				      "timer";

			status = "disabled";

		};

	};

};