Commit 01530775 authored by Wenjun Wu's avatar Wenjun Wu Committed by Jakub Kicinski
Browse files

ice: Support VF queue rate limit and quanta size configuration 



Add support to configure VF queue rate limit and quanta size.

For quanta size configuration, the quanta profiles are divided evenly
by PF numbers. For each port, the first quanta profile is reserved for
default. When VF is asked to set queue quanta size, PF will search for
an available profile, change the fields and assigned this profile to the
queue.

Reviewed-by: default avatarJiri Pirko <jiri@nvidia.com>
Signed-off-by: default avatarWenjun Wu <wenjun1.wu@intel.com>
Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
Link: https://patch.msgid.link/fddefc2c1ec3ab32b241ce444af401da19e834dd.1728460186.git.pabeni@redhat.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 608a5c05

drivers/net/ethernet/intel/ice/ice.h

+2 −0
Original line number Diff line number Diff line
@@ -669,6 +669,8 @@ struct ice_pf { 
	struct ice_agg_node vf_agg_node[ICE_MAX_VF_AGG_NODES];

	struct ice_dplls dplls;

	struct device *hwmon_dev;



	u8 num_quanta_prof_used;

};



extern struct workqueue_struct *ice_lag_wq;

drivers/net/ethernet/intel/ice/ice_base.c

+2 −0
Original line number Diff line number Diff line
@@ -347,6 +347,8 @@ ice_setup_tx_ctx(struct ice_tx_ring *ring, struct ice_tlan_ctx *tlan_ctx, u16 pf 
		break;

	}



	tlan_ctx->quanta_prof_idx = ring->quanta_prof_id;



	tlan_ctx->tso_ena = ICE_TX_LEGACY;

	tlan_ctx->tso_qnum = pf_q;

drivers/net/ethernet/intel/ice/ice_common.c

+21 −0
Original line number Diff line number Diff line
@@ -2436,6 +2436,25 @@ ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 
	ice_recalc_port_limited_caps(hw, &func_p->common_cap);

}



/**

 * ice_func_id_to_logical_id - map from function id to logical pf id

 * @active_function_bitmap: active function bitmap

 * @pf_id: function number of device

 *

 * Return: logical PF ID.

 */

static int ice_func_id_to_logical_id(u32 active_function_bitmap, u8 pf_id)

{

	u8 logical_id = 0;

	u8 i;



	for (i = 0; i < pf_id; i++)

		if (active_function_bitmap & BIT(i))

			logical_id++;



	return logical_id;

}



/**

 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps

 * @hw: pointer to the HW struct
@@ -2453,6 +2472,8 @@ ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 
	dev_p->num_funcs = hweight32(number);

	ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n",

		  dev_p->num_funcs);



	hw->logical_pf_id = ice_func_id_to_logical_id(number, hw->pf_id);

}



/**

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

+8 −0
Original line number Diff line number Diff line
@@ -6,6 +6,14 @@ 
#ifndef _ICE_HW_AUTOGEN_H_

#define _ICE_HW_AUTOGEN_H_



#define GLCOMM_QUANTA_PROF(_i)			(0x002D2D68 + ((_i) * 4))

#define GLCOMM_QUANTA_PROF_MAX_INDEX		15

#define GLCOMM_QUANTA_PROF_QUANTA_SIZE_S	0

#define GLCOMM_QUANTA_PROF_QUANTA_SIZE_M	ICE_M(0x3FFF, 0)

#define GLCOMM_QUANTA_PROF_MAX_CMD_S		16

#define GLCOMM_QUANTA_PROF_MAX_CMD_M		ICE_M(0xFF, 16)

#define GLCOMM_QUANTA_PROF_MAX_DESC_S		24

#define GLCOMM_QUANTA_PROF_MAX_DESC_M		ICE_M(0x3F, 24)

#define QTX_COMM_DBELL(_DBQM)			(0x002C0000 + ((_DBQM) * 4))

#define QTX_COMM_HEAD(_DBQM)			(0x000E0000 + ((_DBQM) * 4))

#define QTX_COMM_HEAD_HEAD_S			0

drivers/net/ethernet/intel/ice/ice_txrx.h

+1 −0
Original line number Diff line number Diff line
@@ -406,6 +406,7 @@ struct ice_tx_ring { 
#define ICE_TX_FLAGS_RING_VLAN_L2TAG2	BIT(2)

	u8 flags;

	u8 dcb_tc;			/* Traffic class of ring */

	u16 quanta_prof_id;

} ____cacheline_internodealigned_in_smp;



static inline bool ice_ring_uses_build_skb(struct ice_rx_ring *ring)