Commit 016f426a authored by Cosmin Ratiu's avatar Cosmin Ratiu Committed by Paolo Abeni
Browse files

net/mlx5: qos: Flesh out element_attributes in mlx5_ifc.h 



This is used for multiple purposes, depending on the scheduling element
created. There are a few helper struct defined a long time ago, but they
are not easy to find in the file and they are about to get new members.
This commit cleans up this area a bit by:
- moving the helper structs closer to where they are relevant.
- defining a helper union to include all of them to help
  discoverability.
- making use of it everywhere element_attributes is used.
- using a consistent 'attr' name.

Signed-off-by: default avatarCosmin Ratiu <cratiu@nvidia.com>
Signed-off-by: default avatarTariq Toukan <tariqt@nvidia.com>
Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parent d9d28b6f

drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c

+8 −10
Original line number Diff line number Diff line
@@ -339,7 +339,7 @@ static int esw_qos_vport_create_sched_element(struct mlx5_eswitch *esw, 
	struct mlx5_esw_rate_group *group = vport->qos.group;

	struct mlx5_core_dev *dev = esw->dev;

	u32 parent_tsar_ix;

	void *vport_elem;

	void *attr;

	int err;



	if (!esw_qos_element_type_supported(dev, SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT))
@@ -348,8 +348,8 @@ static int esw_qos_vport_create_sched_element(struct mlx5_eswitch *esw, 
	parent_tsar_ix = group ? group->tsar_ix : esw->qos.root_tsar_ix;

	MLX5_SET(scheduling_context, sched_ctx, element_type,

		 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT);

	vport_elem = MLX5_ADDR_OF(scheduling_context, sched_ctx, element_attributes);

	MLX5_SET(vport_element, vport_elem, vport_number, vport->vport);

	attr = MLX5_ADDR_OF(scheduling_context, sched_ctx, element_attributes);

	MLX5_SET(vport_element, attr, vport_number, vport->vport);

	MLX5_SET(scheduling_context, sched_ctx, parent_element_id, parent_tsar_ix);

	MLX5_SET(scheduling_context, sched_ctx, max_average_bw, max_rate);

	MLX5_SET(scheduling_context, sched_ctx, bw_share, bw_share);
@@ -443,8 +443,8 @@ __esw_qos_create_rate_group(struct mlx5_eswitch *esw, struct netlink_ext_ack *ex 
{

	u32 tsar_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {};

	struct mlx5_esw_rate_group *group;

	__be32 *attr;

	u32 divider;

	void *attr;

	int err;



	group = kzalloc(sizeof(*group), GFP_KERNEL);
@@ -453,12 +453,10 @@ __esw_qos_create_rate_group(struct mlx5_eswitch *esw, struct netlink_ext_ack *ex 


	MLX5_SET(scheduling_context, tsar_ctx, element_type,

		 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR);



	attr = MLX5_ADDR_OF(scheduling_context, tsar_ctx, element_attributes);

	*attr = cpu_to_be32(TSAR_ELEMENT_TSAR_TYPE_DWRR << 16);



	MLX5_SET(scheduling_context, tsar_ctx, parent_element_id,

		 esw->qos.root_tsar_ix);

	attr = MLX5_ADDR_OF(scheduling_context, tsar_ctx, element_attributes);

	MLX5_SET(tsar_element, attr, tsar_type, TSAR_ELEMENT_TSAR_TYPE_DWRR);

	err = mlx5_create_scheduling_element_cmd(esw->dev,

						 SCHEDULING_HIERARCHY_E_SWITCH,

						 tsar_ctx,
@@ -559,7 +557,7 @@ static int esw_qos_create(struct mlx5_eswitch *esw, struct netlink_ext_ack *exta 
{

	u32 tsar_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {};

	struct mlx5_core_dev *dev = esw->dev;

	__be32 *attr;

	void *attr;

	int err;



	if (!MLX5_CAP_GEN(dev, qos) || !MLX5_CAP_QOS(dev, esw_scheduling))
@@ -573,7 +571,7 @@ static int esw_qos_create(struct mlx5_eswitch *esw, struct netlink_ext_ack *exta 
		 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR);



	attr = MLX5_ADDR_OF(scheduling_context, tsar_ctx, element_attributes);

	*attr = cpu_to_be32(TSAR_ELEMENT_TSAR_TYPE_DWRR << 16);

	MLX5_SET(tsar_element, attr, tsar_type, TSAR_ELEMENT_TSAR_TYPE_DWRR);



	err = mlx5_create_scheduling_element_cmd(dev,

						 SCHEDULING_HIERARCHY_E_SWITCH,

include/linux/mlx5/mlx5_ifc.h

+37 −30
Original line number Diff line number Diff line
@@ -4105,11 +4105,47 @@ enum { 
	ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP	= 1 << 4,

};



enum {

	TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,

	TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,

	TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,

};



enum {

	TSAR_TYPE_CAP_MASK_DWRR		= 1 << 0,

	TSAR_TYPE_CAP_MASK_ROUND_ROBIN	= 1 << 1,

	TSAR_TYPE_CAP_MASK_ETS		= 1 << 2,

};



struct mlx5_ifc_tsar_element_bits {

	u8         reserved_at_0[0x8];

	u8         tsar_type[0x8];

	u8         reserved_at_10[0x10];

};



struct mlx5_ifc_vport_element_bits {

	u8         reserved_at_0[0x10];

	u8         vport_number[0x10];

};



struct mlx5_ifc_vport_tc_element_bits {

	u8         traffic_class[0x4];

	u8         reserved_at_4[0xc];

	u8         vport_number[0x10];

};



union mlx5_ifc_element_attributes_bits {

	struct mlx5_ifc_tsar_element_bits tsar;

	struct mlx5_ifc_vport_element_bits vport;

	struct mlx5_ifc_vport_tc_element_bits vport_tc;

	u8 reserved_at_0[0x20];

};



struct mlx5_ifc_scheduling_context_bits {

	u8         element_type[0x8];

	u8         reserved_at_8[0x18];



	u8         element_attributes[0x20];

	union mlx5_ifc_element_attributes_bits element_attributes;



	u8         parent_element_id[0x20];
@@ -4798,35 +4834,6 @@ struct mlx5_ifc_register_loopback_control_bits { 
	u8         reserved_at_20[0x60];

};



struct mlx5_ifc_vport_tc_element_bits {

	u8         traffic_class[0x4];

	u8         reserved_at_4[0xc];

	u8         vport_number[0x10];

};



struct mlx5_ifc_vport_element_bits {

	u8         reserved_at_0[0x10];

	u8         vport_number[0x10];

};



enum {

	TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,

	TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,

	TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,

};



enum {

	TSAR_TYPE_CAP_MASK_DWRR		= 1 << 0,

	TSAR_TYPE_CAP_MASK_ROUND_ROBIN	= 1 << 1,

	TSAR_TYPE_CAP_MASK_ETS		= 1 << 2,

};



struct mlx5_ifc_tsar_element_bits {

	u8         reserved_at_0[0x8];

	u8         tsar_type[0x8];

	u8         reserved_at_10[0x10];

};



enum {

	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,

	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,