Commit 01785f1f authored by Peng Fan's avatar Peng Fan Committed by Shawn Guo
Browse files

arm64: dts: imx8mp-evk: correct mmc pad settings 



According to RM bit layout, BIT3 and BIT0 are reserved.
  8  7   6   5   4   3  2 1  0
 PE HYS PUE ODE FSEL X  DSE  X

Not set reserved bit.

Fixes: 9e847693 ("arm64: dts: freescale: Add i.MX8MP EVK board support")
Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Reviewed-by: default avatarRasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent b10ef5f2

arch/arm64/boot/dts/freescale/imx8mp-evk.dts

+4 −4
Original line number Diff line number Diff line
@@ -500,7 +500,7 @@ MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* Input pull-up. */ 


	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {

		fsl,pins = <

			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x41

			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40

		>;

	};
@@ -525,7 +525,7 @@ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0

			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0

			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0

			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1

			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0

		>;

	};
@@ -537,7 +537,7 @@ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4

			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4

			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4

			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1

			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0

		>;

	};
@@ -549,7 +549,7 @@ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6

			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6

			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6

			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1

			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0

		>;

	};