Commit 0185fbc6 authored by Christoph Schlameuss's avatar Christoph Schlameuss Committed by Janosch Frank
Browse files

KVM: s390: selftests: Add uc_skey VM test case 



Add a test case manipulating s390 storage keys from within the ucontrol
VM.

Storage key instruction (ISKE, SSKE and RRBE) intercepts and
Keyless-subset facility are disabled on first use, where the skeys are
setup by KVM in non ucontrol VMs.

Signed-off-by: default avatarChristoph Schlameuss <schlameuss@linux.ibm.com>
Link: https://lore.kernel.org/r/20241108091620.289406-1-schlameuss@linux.ibm.com


Acked-by: default avatarJanosch Frank <frankja@linux.ibm.com>
[frankja@linux.ibm.com: Fixed patch prefix]
Signed-off-by: default avatarJanosch Frank <frankja@linux.ibm.com>
Message-ID: <20241108091620.289406-1-schlameuss@linux.ibm.com>
parent ae16b0ab

tools/testing/selftests/kvm/include/s390x/processor.h

+6 −0
Original line number Diff line number Diff line
@@ -32,4 +32,10 @@ static inline void cpu_relax(void) 
	barrier();

}



/* Get the instruction length */

static inline int insn_length(unsigned char code)

{

	return ((((int)code + 64) >> 7) + 1) << 1;

}



#endif

tools/testing/selftests/kvm/s390x/ucontrol_test.c

+143 −2
Original line number Diff line number Diff line
@@ -79,6 +79,33 @@ asm("test_mem_asm:\n" 
	"	j	0b\n"

);



/* Test program manipulating storage keys */

extern char test_skey_asm[];

asm("test_skey_asm:\n"

	"xgr	%r0, %r0\n"



	"0:\n"

	"	ahi	%r0,1\n"

	"	st	%r1,0(%r5,%r6)\n"



	"	iske	%r1,%r6\n"

	"	ahi	%r0,1\n"

	"	diag	0,0,0x44\n"



	"	sske	%r1,%r6\n"

	"	xgr	%r1,%r1\n"

	"	iske	%r1,%r6\n"

	"	ahi	%r0,1\n"

	"	diag	0,0,0x44\n"



	"	rrbe	%r1,%r6\n"

	"	iske	%r1,%r6\n"

	"	ahi	%r0,1\n"

	"	diag	0,0,0x44\n"



	"	j	0b\n"

);



FIXTURE(uc_kvm)

{

	struct kvm_s390_sie_block *sie_block;
@@ -298,8 +325,50 @@ static void uc_handle_exit_ucontrol(FIXTURE_DATA(uc_kvm) *self) 
	}

}



/* verify SIEIC exit

/*

 * Handle the SIEIC exit

 * * fail on codes not expected in the test cases

 * Returns if interception is handled / execution can be continued

 */

static void uc_skey_enable(FIXTURE_DATA(uc_kvm) *self)

{

	struct kvm_s390_sie_block *sie_block = self->sie_block;



	/* disable KSS */

	sie_block->cpuflags &= ~CPUSTAT_KSS;

	/* disable skey inst interception */

	sie_block->ictl &= ~(ICTL_ISKE | ICTL_SSKE | ICTL_RRBE);

}



/*

 * Handle the instruction intercept

 * Returns if interception is handled / execution can be continued

 */

static bool uc_handle_insn_ic(FIXTURE_DATA(uc_kvm) *self)

{

	struct kvm_s390_sie_block *sie_block = self->sie_block;

	int ilen = insn_length(sie_block->ipa >> 8);

	struct kvm_run *run = self->run;



	switch (run->s390_sieic.ipa) {

	case 0xB229: /* ISKE */

	case 0xB22b: /* SSKE */

	case 0xB22a: /* RRBE */

		uc_skey_enable(self);



		/* rewind to reexecute intercepted instruction */

		run->psw_addr = run->psw_addr - ilen;

		pr_info("rewind guest addr to 0x%.16llx\n", run->psw_addr);

		return true;

	default:

		return false;

	}

}



/*

 * Handle the SIEIC exit

 * * fail on codes not expected in the test cases

 * Returns if interception is handled / execution can be continued

 */

static bool uc_handle_sieic(FIXTURE_DATA(uc_kvm) * self)

{
@@ -315,7 +384,10 @@ static bool uc_handle_sieic(FIXTURE_DATA(uc_kvm) * self) 
	case ICPT_INST:

		/* end execution in caller on intercepted instruction */

		pr_info("sie instruction interception\n");

		return false;

		return uc_handle_insn_ic(self);

	case ICPT_KSS:

		uc_skey_enable(self);

		return true;

	case ICPT_OPEREXC:

		/* operation exception */

		TEST_FAIL("sie exception on %.4x%.8x", sie_block->ipa, sie_block->ipb);
@@ -472,4 +544,73 @@ TEST_F(uc_kvm, uc_gprs) 
	ASSERT_EQ(1, sync_regs->gprs[0]);

}



TEST_F(uc_kvm, uc_skey)

{

	struct kvm_s390_sie_block *sie_block = self->sie_block;

	struct kvm_sync_regs *sync_regs = &self->run->s.regs;

	u64 test_vaddr = VM_MEM_SIZE - (SZ_1M / 2);

	struct kvm_run *run = self->run;

	const u8 skeyvalue = 0x34;



	/* copy test_skey_asm to code_hva / code_gpa */

	TH_LOG("copy code %p to vm mapped memory %p / %p",

	       &test_skey_asm, (void *)self->code_hva, (void *)self->code_gpa);

	memcpy((void *)self->code_hva, &test_skey_asm, PAGE_SIZE);



	/* set register content for test_skey_asm to access not mapped memory */

	sync_regs->gprs[1] = skeyvalue;

	sync_regs->gprs[5] = self->base_gpa;

	sync_regs->gprs[6] = test_vaddr;

	run->kvm_dirty_regs |= KVM_SYNC_GPRS;



	/* DAT disabled + 64 bit mode */

	run->psw_mask = 0x0000000180000000ULL;

	run->psw_addr = self->code_gpa;



	ASSERT_EQ(0, uc_run_once(self));

	ASSERT_EQ(true, uc_handle_exit(self));

	ASSERT_EQ(1, sync_regs->gprs[0]);



	/* ISKE */

	ASSERT_EQ(0, uc_run_once(self));



	/*

	 * Bail out and skip the test after uc_skey_enable was executed but iske

	 * is still intercepted. Instructions are not handled by the kernel.

	 * Thus there is no need to test this here.

	 */

	TEST_ASSERT_EQ(0, sie_block->cpuflags & CPUSTAT_KSS);

	TEST_ASSERT_EQ(0, sie_block->ictl & (ICTL_ISKE | ICTL_SSKE | ICTL_RRBE));

	TEST_ASSERT_EQ(KVM_EXIT_S390_SIEIC, self->run->exit_reason);

	TEST_ASSERT_EQ(ICPT_INST, sie_block->icptcode);

	TEST_REQUIRE(sie_block->ipa != 0xb229);



	/* ISKE contd. */

	ASSERT_EQ(false, uc_handle_exit(self));

	ASSERT_EQ(2, sync_regs->gprs[0]);

	/* assert initial skey (ACC = 0, R & C = 1) */

	ASSERT_EQ(0x06, sync_regs->gprs[1]);

	uc_assert_diag44(self);



	/* SSKE + ISKE */

	sync_regs->gprs[1] = skeyvalue;

	run->kvm_dirty_regs |= KVM_SYNC_GPRS;

	ASSERT_EQ(0, uc_run_once(self));

	ASSERT_EQ(false, uc_handle_exit(self));

	ASSERT_EQ(3, sync_regs->gprs[0]);

	ASSERT_EQ(skeyvalue, sync_regs->gprs[1]);

	uc_assert_diag44(self);



	/* RRBE + ISKE */

	sync_regs->gprs[1] = skeyvalue;

	run->kvm_dirty_regs |= KVM_SYNC_GPRS;

	ASSERT_EQ(0, uc_run_once(self));

	ASSERT_EQ(false, uc_handle_exit(self));

	ASSERT_EQ(4, sync_regs->gprs[0]);

	/* assert R reset but rest of skey unchanged */

	ASSERT_EQ(skeyvalue & 0xfa, sync_regs->gprs[1]);

	ASSERT_EQ(0, sync_regs->gprs[1] & 0x04);

	uc_assert_diag44(self);

}



TEST_HARNESS_MAIN