Commit 01cb5e3d authored by Ian Rogers's avatar Ian Rogers Committed by Namhyung Kim
Browse files

perf vendor events: Update sandybridge metrics add event counter information 

Add counter information necessary for optimizing event grouping the
perf tool.

The most recent RFC patch set using this information:
https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/

The information was added in:
https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4765e1
and later patches.

The TMA 4.8 information was updated in:
https://github.com/intel/perfmon/commit/59194d4d90ca50a3fcb2de0d82b9f6fc0c9a5736



Co-authored-by: default avatarWeilin Wang <weilin.wang@intel.com>
Co-authored-by: default avatarCaleb Biggers <caleb.biggers@intel.com>
Signed-off-by: default avatarIan Rogers <irogers@google.com>
Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: default avatarNamhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/r/20240620181752.3945845-28-irogers@google.com
parent bf0dd1f4

tools/perf/pmu-events/arch/x86/sandybridge/cache.json

+173 −0

File changed.

Preview size limit exceeded, changes collapsed.

tools/perf/pmu-events/arch/x86/sandybridge/counter.json

0 → 100644
+17 −0
Original line number Diff line number Diff line 
[

    {

        "Unit": "core",

        "CountersNumFixed": "3",

        "CountersNumGeneric": "4"

    },

    {

        "Unit": "ARB",

        "CountersNumFixed": "1",

        "CountersNumGeneric": "2"

    },

    {

        "Unit": "CBOX",

        "CountersNumFixed": "0",

        "CountersNumGeneric": "2"

    }

]
 
 No newline at end of file

tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json

+15 −0
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Cycles with any input/output SSE or FP assist.",

        "Counter": "0,1,2,3",

        "CounterMask": "1",

        "EventCode": "0xCA",

        "EventName": "FP_ASSIST.ANY",
@@ -9,6 +10,7 @@ 
    },

    {

        "BriefDescription": "Number of SIMD FP assists due to input values.",

        "Counter": "0,1,2,3",

        "EventCode": "0xCA",

        "EventName": "FP_ASSIST.SIMD_INPUT",

        "SampleAfterValue": "100003",
@@ -16,6 +18,7 @@ 
    },

    {

        "BriefDescription": "Number of SIMD FP assists due to Output values.",

        "Counter": "0,1,2,3",

        "EventCode": "0xCA",

        "EventName": "FP_ASSIST.SIMD_OUTPUT",

        "SampleAfterValue": "100003",
@@ -23,6 +26,7 @@ 
    },

    {

        "BriefDescription": "Number of X87 assists due to input value.",

        "Counter": "0,1,2,3",

        "EventCode": "0xCA",

        "EventName": "FP_ASSIST.X87_INPUT",

        "SampleAfterValue": "100003",
@@ -30,6 +34,7 @@ 
    },

    {

        "BriefDescription": "Number of X87 assists due to output value.",

        "Counter": "0,1,2,3",

        "EventCode": "0xCA",

        "EventName": "FP_ASSIST.X87_OUTPUT",

        "SampleAfterValue": "100003",
@@ -37,6 +42,7 @@ 
    },

    {

        "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.",

        "Counter": "0,1,2,3",

        "EventCode": "0x10",

        "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE",

        "SampleAfterValue": "2000003",
@@ -44,6 +50,7 @@ 
    },

    {

        "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.",

        "Counter": "0,1,2,3",

        "EventCode": "0x10",

        "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE",

        "SampleAfterValue": "2000003",
@@ -51,6 +58,7 @@ 
    },

    {

        "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle.",

        "Counter": "0,1,2,3",

        "EventCode": "0x10",

        "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE",

        "SampleAfterValue": "2000003",
@@ -58,6 +66,7 @@ 
    },

    {

        "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.",

        "Counter": "0,1,2,3",

        "EventCode": "0x10",

        "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE",

        "SampleAfterValue": "2000003",
@@ -65,6 +74,7 @@ 
    },

    {

        "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULs and IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.",

        "Counter": "0,1,2,3",

        "EventCode": "0x10",

        "EventName": "FP_COMP_OPS_EXE.X87",

        "SampleAfterValue": "2000003",
@@ -72,6 +82,7 @@ 
    },

    {

        "BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",

        "Counter": "0,1,2,3",

        "EventCode": "0xC1",

        "EventName": "OTHER_ASSISTS.AVX_STORE",

        "SampleAfterValue": "100003",
@@ -79,6 +90,7 @@ 
    },

    {

        "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",

        "Counter": "0,1,2,3",

        "EventCode": "0xC1",

        "EventName": "OTHER_ASSISTS.AVX_TO_SSE",

        "SampleAfterValue": "100003",
@@ -86,6 +98,7 @@ 
    },

    {

        "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",

        "Counter": "0,1,2,3",

        "EventCode": "0xC1",

        "EventName": "OTHER_ASSISTS.SSE_TO_AVX",

        "SampleAfterValue": "100003",
@@ -93,6 +106,7 @@ 
    },

    {

        "BriefDescription": "Number of AVX-256 Computational FP double precision uops issued this cycle.",

        "Counter": "0,1,2,3",

        "EventCode": "0x11",

        "EventName": "SIMD_FP_256.PACKED_DOUBLE",

        "SampleAfterValue": "2000003",
@@ -100,6 +114,7 @@ 
    },

    {

        "BriefDescription": "Number of GSSE-256 Computational FP single precision uops issued this cycle.",

        "Counter": "0,1,2,3",

        "EventCode": "0x11",

        "EventName": "SIMD_FP_256.PACKED_SINGLE",

        "SampleAfterValue": "2000003",

tools/perf/pmu-events/arch/x86/sandybridge/frontend.json

+32 −0
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",

        "Counter": "0,1,2,3",

        "EventCode": "0xE6",

        "EventName": "BACLEARS.ANY",

        "SampleAfterValue": "100003",
@@ -8,6 +9,7 @@ 
    },

    {

        "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.",

        "Counter": "0,1,2,3",

        "EventCode": "0xAB",

        "EventName": "DSB2MITE_SWITCHES.COUNT",

        "SampleAfterValue": "2000003",
@@ -15,6 +17,7 @@ 
    },

    {

        "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",

        "Counter": "0,1,2,3",

        "EventCode": "0xAB",

        "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",

        "PublicDescription": "This event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline.  It excludes cycles when the back-end cannot  accept new micro-ops.  The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-end.",
@@ -23,6 +26,7 @@ 
    },

    {

        "BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit.",

        "Counter": "0,1,2,3",

        "EventCode": "0xAC",

        "EventName": "DSB_FILL.ALL_CANCEL",

        "SampleAfterValue": "2000003",
@@ -30,6 +34,7 @@ 
    },

    {

        "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines.",

        "Counter": "0,1,2,3",

        "EventCode": "0xAC",

        "EventName": "DSB_FILL.EXCEED_DSB_LINES",

        "SampleAfterValue": "2000003",
@@ -37,6 +42,7 @@ 
    },

    {

        "BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.",

        "Counter": "0,1,2,3",

        "EventCode": "0xAC",

        "EventName": "DSB_FILL.OTHER_CANCEL",

        "SampleAfterValue": "2000003",
@@ -44,6 +50,7 @@ 
    },

    {

        "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",

        "Counter": "0,1,2,3",

        "EventCode": "0x80",

        "EventName": "ICACHE.HIT",

        "SampleAfterValue": "2000003",
@@ -51,6 +58,7 @@ 
    },

    {

        "BriefDescription": "Instruction cache, streaming buffer and victim cache misses.",

        "Counter": "0,1,2,3",

        "EventCode": "0x80",

        "EventName": "ICACHE.MISSES",

        "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses.",
@@ -59,6 +67,7 @@ 
    },

    {

        "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.",

        "Counter": "0,1,2,3",

        "CounterMask": "4",

        "EventCode": "0x79",

        "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
@@ -67,6 +76,7 @@ 
    },

    {

        "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.",

        "Counter": "0,1,2,3",

        "CounterMask": "1",

        "EventCode": "0x79",

        "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
@@ -75,6 +85,7 @@ 
    },

    {

        "BriefDescription": "Cycles MITE is delivering 4 Uops.",

        "Counter": "0,1,2,3",

        "CounterMask": "4",

        "EventCode": "0x79",

        "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
@@ -83,6 +94,7 @@ 
    },

    {

        "BriefDescription": "Cycles MITE is delivering any Uop.",

        "Counter": "0,1,2,3",

        "CounterMask": "1",

        "EventCode": "0x79",

        "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
@@ -91,6 +103,7 @@ 
    },

    {

        "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",

        "Counter": "0,1,2,3",

        "CounterMask": "1",

        "EventCode": "0x79",

        "EventName": "IDQ.DSB_CYCLES",
@@ -99,6 +112,7 @@ 
    },

    {

        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",

        "Counter": "0,1,2,3",

        "EventCode": "0x79",

        "EventName": "IDQ.DSB_UOPS",

        "SampleAfterValue": "2000003",
@@ -106,6 +120,7 @@ 
    },

    {

        "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles.",

        "Counter": "0,1,2,3",

        "EventCode": "0x79",

        "EventName": "IDQ.EMPTY",

        "SampleAfterValue": "2000003",
@@ -113,6 +128,7 @@ 
    },

    {

        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.",

        "Counter": "0,1,2,3",

        "EventCode": "0x79",

        "EventName": "IDQ.MITE_ALL_UOPS",

        "SampleAfterValue": "2000003",
@@ -120,6 +136,7 @@ 
    },

    {

        "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",

        "Counter": "0,1,2,3",

        "CounterMask": "1",

        "EventCode": "0x79",

        "EventName": "IDQ.MITE_CYCLES",
@@ -128,6 +145,7 @@ 
    },

    {

        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.",

        "Counter": "0,1,2,3",

        "EventCode": "0x79",

        "EventName": "IDQ.MITE_UOPS",

        "SampleAfterValue": "2000003",
@@ -135,6 +153,7 @@ 
    },

    {

        "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",

        "Counter": "0,1,2,3",

        "CounterMask": "1",

        "EventCode": "0x79",

        "EventName": "IDQ.MS_CYCLES",
@@ -144,6 +163,7 @@ 
    },

    {

        "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",

        "Counter": "0,1,2,3",

        "CounterMask": "1",

        "EventCode": "0x79",

        "EventName": "IDQ.MS_DSB_CYCLES",
@@ -152,6 +172,7 @@ 
    },

    {

        "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy.",

        "Counter": "0,1,2,3",

        "CounterMask": "1",

        "EdgeDetect": "1",

        "EventCode": "0x79",
@@ -161,6 +182,7 @@ 
    },

    {

        "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",

        "Counter": "0,1,2,3",

        "EventCode": "0x79",

        "EventName": "IDQ.MS_DSB_UOPS",

        "SampleAfterValue": "2000003",
@@ -168,6 +190,7 @@ 
    },

    {

        "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",

        "Counter": "0,1,2,3",

        "EventCode": "0x79",

        "EventName": "IDQ.MS_MITE_UOPS",

        "SampleAfterValue": "2000003",
@@ -175,6 +198,7 @@ 
    },

    {

        "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",

        "Counter": "0,1,2,3",

        "CounterMask": "1",

        "EdgeDetect": "1",

        "EventCode": "0x79",
@@ -184,6 +208,7 @@ 
    },

    {

        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",

        "Counter": "0,1,2,3",

        "EventCode": "0x79",

        "EventName": "IDQ.MS_UOPS",

        "SampleAfterValue": "2000003",
@@ -191,6 +216,7 @@ 
    },

    {

        "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled .",

        "Counter": "0,1,2,3",

        "EventCode": "0x9C",

        "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",

        "PublicDescription": "This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled.  In the ideal case 4 uops can be delivered each cycle.  The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them.  This event is used in determining the front-end bound category of the top-down pipeline slots characterization.",
@@ -199,6 +225,7 @@ 
    },

    {

        "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",

        "Counter": "0,1,2,3",

        "CounterMask": "4",

        "EventCode": "0x9C",

        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
@@ -207,6 +234,7 @@ 
    },

    {

        "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",

        "Counter": "0,1,2,3",

        "CounterMask": "1",

        "EventCode": "0x9C",

        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
@@ -216,6 +244,7 @@ 
    },

    {

        "BriefDescription": "Cycles when 1 or more uops were delivered to the by the front end.",

        "Counter": "0,1,2,3",

        "CounterMask": "4",

        "EventCode": "0x9C",

        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE",
@@ -225,6 +254,7 @@ 
    },

    {

        "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",

        "Counter": "0,1,2,3",

        "CounterMask": "3",

        "EventCode": "0x9C",

        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
@@ -233,6 +263,7 @@ 
    },

    {

        "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",

        "Counter": "0,1,2,3",

        "CounterMask": "2",

        "EventCode": "0x9C",

        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
@@ -241,6 +272,7 @@ 
    },

    {

        "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",

        "Counter": "0,1,2,3",

        "CounterMask": "1",

        "EventCode": "0x9C",

        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",

tools/perf/pmu-events/arch/x86/sandybridge/memory.json

+37 −0
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",

        "Counter": "0,1,2,3",

        "EventCode": "0xC3",

        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",

        "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers.  Machine clears can have a significant performance impact if they are happening frequently.",
@@ -9,6 +10,7 @@ 
    },

    {

        "BriefDescription": "Loads with latency value being above 128.",

        "Counter": "3",

        "EventCode": "0xCD",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",

        "MSRIndex": "0x3F6",
@@ -19,6 +21,7 @@ 
    },

    {

        "BriefDescription": "Loads with latency value being above 16.",

        "Counter": "3",

        "EventCode": "0xCD",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",

        "MSRIndex": "0x3F6",
@@ -29,6 +32,7 @@ 
    },

    {

        "BriefDescription": "Loads with latency value being above 256.",

        "Counter": "3",

        "EventCode": "0xCD",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",

        "MSRIndex": "0x3F6",
@@ -39,6 +43,7 @@ 
    },

    {

        "BriefDescription": "Loads with latency value being above 32.",

        "Counter": "3",

        "EventCode": "0xCD",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",

        "MSRIndex": "0x3F6",
@@ -49,6 +54,7 @@ 
    },

    {

        "BriefDescription": "Loads with latency value being above 4 .",

        "Counter": "3",

        "EventCode": "0xCD",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",

        "MSRIndex": "0x3F6",
@@ -59,6 +65,7 @@ 
    },

    {

        "BriefDescription": "Loads with latency value being above 512.",

        "Counter": "3",

        "EventCode": "0xCD",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",

        "MSRIndex": "0x3F6",
@@ -69,6 +76,7 @@ 
    },

    {

        "BriefDescription": "Loads with latency value being above 64.",

        "Counter": "3",

        "EventCode": "0xCD",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",

        "MSRIndex": "0x3F6",
@@ -79,6 +87,7 @@ 
    },

    {

        "BriefDescription": "Loads with latency value being above 8.",

        "Counter": "3",

        "EventCode": "0xCD",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",

        "MSRIndex": "0x3F6",
@@ -89,6 +98,7 @@ 
    },

    {

        "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).",

        "Counter": "3",

        "EventCode": "0xCD",

        "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",

        "PEBS": "2",
@@ -97,6 +107,7 @@ 
    },

    {

        "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0x05",

        "EventName": "MISALIGN_MEM_REF.LOADS",

        "SampleAfterValue": "2000003",
@@ -104,6 +115,7 @@ 
    },

    {

        "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0x05",

        "EventName": "MISALIGN_MEM_REF.STORES",

        "SampleAfterValue": "2000003",
@@ -111,6 +123,7 @@ 
    },

    {

        "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC  and the data returned from dram.",

        "Counter": "0,1,2,3",

        "EventCode": "0xB7, 0xBB",

        "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM",

        "MSRIndex": "0x1a6,0x1a7",
@@ -120,6 +133,7 @@ 
    },

    {

        "BriefDescription": "Counts all demand & prefetch data reads that miss the LLC  and the data returned from dram.",

        "Counter": "0,1,2,3",

        "EventCode": "0xB7, 0xBB",

        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM",

        "MSRIndex": "0x1a6,0x1a7",
@@ -129,6 +143,7 @@ 
    },

    {

        "BriefDescription": "Counts all prefetch code reads that miss the LLC  and the data returned from dram.",

        "Counter": "0,1,2,3",

        "EventCode": "0xB7, 0xBB",

        "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_MISS.DRAM",

        "MSRIndex": "0x1a6,0x1a7",
@@ -138,6 +153,7 @@ 
    },

    {

        "BriefDescription": "Counts all prefetch data reads that miss the LLC  and the data returned from dram.",

        "Counter": "0,1,2,3",

        "EventCode": "0xB7, 0xBB",

        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_MISS.DRAM",

        "MSRIndex": "0x1a6,0x1a7",
@@ -147,6 +163,7 @@ 
    },

    {

        "BriefDescription": "Counts all prefetch RFOs that miss the LLC  and the data returned from dram.",

        "Counter": "0,1,2,3",

        "EventCode": "0xB7, 0xBB",

        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_MISS.DRAM",

        "MSRIndex": "0x1a6,0x1a7",
@@ -156,6 +173,7 @@ 
    },

    {

        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data returned from dram.",

        "Counter": "0,1,2,3",

        "EventCode": "0xB7, 0xBB",

        "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM",

        "MSRIndex": "0x1a6,0x1a7",
@@ -165,6 +183,7 @@ 
    },

    {

        "BriefDescription": "Counts all demand & prefetch RFOs that miss the LLC  and the data returned from dram.",

        "Counter": "0,1,2,3",

        "EventCode": "0xB7, 0xBB",

        "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.DRAM",

        "MSRIndex": "0x1a6,0x1a7",
@@ -174,6 +193,7 @@ 
    },

    {

        "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",

        "Counter": "0,1,2,3",

        "EventCode": "0xB7, 0xBB",

        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_MISS_LOCAL.DRAM",

        "MSRIndex": "0x1a6,0x1a7",
@@ -184,6 +204,7 @@ 
    },

    {

        "BriefDescription": "Counts LLC replacements.",

        "Counter": "0,1,2,3",

        "EventCode": "0xB7, 0xBB",

        "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM",

        "MSRIndex": "0x1a6,0x1a7",
@@ -194,6 +215,7 @@ 
    },

    {

        "BriefDescription": "REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIT",

        "Counter": "0,1,2,3",

        "EventCode": "0xB7, 0xBB",

        "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS_LOCAL.ANY_LLC_HIT",

        "MSRIndex": "0x1a6,0x1a7",
@@ -203,6 +225,7 @@ 
    },

    {

        "BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram.",

        "Counter": "0,1,2,3",

        "EventCode": "0xB7, 0xBB",

        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM",

        "MSRIndex": "0x1a6,0x1a7",
@@ -212,6 +235,7 @@ 
    },

    {

        "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram.",

        "Counter": "0,1,2,3",

        "EventCode": "0xB7, 0xBB",

        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM",

        "MSRIndex": "0x1a6,0x1a7",
@@ -221,6 +245,7 @@ 
    },

    {

        "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",

        "Counter": "0,1,2,3",

        "EventCode": "0xB7, 0xBB",

        "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_MISS_LOCAL.DRAM",

        "MSRIndex": "0x1a6,0x1a7",
@@ -230,6 +255,7 @@ 
    },

    {

        "BriefDescription": "Counts demand data writes (RFOs) that miss the LLC and the data returned from dram.",

        "Counter": "0,1,2,3",

        "EventCode": "0xB7, 0xBB",

        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.DRAM",

        "MSRIndex": "0x1a6,0x1a7",
@@ -239,6 +265,7 @@ 
    },

    {

        "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",

        "Counter": "0,1,2,3",

        "EventCode": "0xB7, 0xBB",

        "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_MISS_LOCAL.DRAM",

        "MSRIndex": "0x1a6,0x1a7",
@@ -248,6 +275,7 @@ 
    },

    {

        "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",

        "Counter": "0,1,2,3",

        "EventCode": "0xB7, 0xBB",

        "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_MISS_LOCAL.DRAM",

        "MSRIndex": "0x1a6,0x1a7",
@@ -257,6 +285,7 @@ 
    },

    {

        "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC  and the data returned from dram.",

        "Counter": "0,1,2,3",

        "EventCode": "0xB7, 0xBB",

        "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.DRAM",

        "MSRIndex": "0x1a6,0x1a7",
@@ -266,6 +295,7 @@ 
    },

    {

        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from dram.",

        "Counter": "0,1,2,3",

        "EventCode": "0xB7, 0xBB",

        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.DRAM",

        "MSRIndex": "0x1a6,0x1a7",
@@ -275,6 +305,7 @@ 
    },

    {

        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the LLC  and the data returned from dram.",

        "Counter": "0,1,2,3",

        "EventCode": "0xB7, 0xBB",

        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.DRAM",

        "MSRIndex": "0x1a6,0x1a7",
@@ -284,6 +315,7 @@ 
    },

    {

        "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss the LLC  and the data returned from dram.",

        "Counter": "0,1,2,3",

        "EventCode": "0xB7, 0xBB",

        "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.DRAM",

        "MSRIndex": "0x1a6,0x1a7",
@@ -293,6 +325,7 @@ 
    },

    {

        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the LLC  and the data returned from dram.",

        "Counter": "0,1,2,3",

        "EventCode": "0xB7, 0xBB",

        "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.DRAM",

        "MSRIndex": "0x1a6,0x1a7",
@@ -302,6 +335,7 @@ 
    },

    {

        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC  and the data returned from dram.",

        "Counter": "0,1,2,3",

        "EventCode": "0xB7, 0xBB",

        "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.DRAM",

        "MSRIndex": "0x1a6,0x1a7",
@@ -311,6 +345,7 @@ 
    },

    {

        "BriefDescription": "REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",

        "Counter": "0,1,2,3",

        "EventCode": "0xB7, 0xBB",

        "EventName": "OFFCORE_RESPONSE.PF_L_DATA_RD.LLC_MISS_LOCAL.DRAM",

        "MSRIndex": "0x1a6,0x1a7",
@@ -320,6 +355,7 @@ 
    },

    {

        "BriefDescription": "REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",

        "Counter": "0,1,2,3",

        "EventCode": "0xB7, 0xBB",

        "EventName": "OFFCORE_RESPONSE.PF_L_IFETCH.LLC_MISS_LOCAL.DRAM",

        "MSRIndex": "0x1a6,0x1a7",
@@ -329,6 +365,7 @@ 
    },

    {

        "BriefDescription": "Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND.",

        "Counter": "0,1,2,3",

        "EventCode": "0xBE",

        "EventName": "PAGE_WALKS.LLC_MISS",

        "SampleAfterValue": "100003",