Commit 01e0cfc9 authored by Thomas Hellström's avatar Thomas Hellström
Browse files

drm/xe: Use write-back caching mode for system memory on DGFX 



The caching mode for buffer objects with VRAM as a possible
placement was forced to write-combined, regardless of placement.

However, write-combined system memory is expensive to allocate and
even though it is pooled, the pool is expensive to shrink, since
it involves global CPU TLB flushes.

Moreover write-combined system memory from TTM is only reliably
available on x86 and DGFX doesn't have an x86 restriction.

So regardless of the cpu caching mode selected for a bo,
internally use write-back caching mode for system memory on DGFX.

Coherency is maintained, but user-space clients may perceive a
difference in cpu access speeds.

v2:
- Update RB- and Ack tags.
- Rephrase wording in xe_drm.h (Matt Roper)
v3:
- Really rephrase wording.

Signed-off-by: default avatarThomas Hellström <thomas.hellstrom@linux.intel.com>
Fixes: 622f709c ("drm/xe/uapi: Add support for CPU caching mode")
Cc: Pallavi Mishra <pallavi.mishra@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: dri-devel@lists.freedesktop.org
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Effie Yu <effie.yu@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Jose Souza <jose.souza@intel.com>
Cc: Michal Mrozek <michal.mrozek@intel.com>
Cc: <stable@vger.kernel.org> # v6.8+
Acked-by: default avatarMatthew Auld <matthew.auld@intel.com>
Acked-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Fixes: 622f709c ("drm/xe/uapi: Add support for CPU caching mode")
Acked-by: default avatarMichal Mrozek <michal.mrozek@intel.com>
Acked-by: Effie Yu <effie.yu@intel.com> #On chat
Link: https://patchwork.freedesktop.org/patch/msgid/20240705132828.27714-1-thomas.hellstrom@linux.intel.com
parent c55f79f3

drivers/gpu/drm/xe/xe_bo.c

+28 −19
Original line number Diff line number Diff line
@@ -343,7 +343,7 @@ static struct ttm_tt *xe_ttm_tt_create(struct ttm_buffer_object *ttm_bo, 
	struct xe_device *xe = xe_bo_device(bo);

	struct xe_ttm_tt *tt;

	unsigned long extra_pages;

	enum ttm_caching caching;

	enum ttm_caching caching = ttm_cached;

	int err;



	tt = kzalloc(sizeof(*tt), GFP_KERNEL);
@@ -357,6 +357,13 @@ static struct ttm_tt *xe_ttm_tt_create(struct ttm_buffer_object *ttm_bo, 
		extra_pages = DIV_ROUND_UP(xe_device_ccs_bytes(xe, bo->size),

					   PAGE_SIZE);



	/*

	 * DGFX system memory is always WB / ttm_cached, since

	 * other caching modes are only supported on x86. DGFX

	 * GPU system memory accesses are always coherent with the

	 * CPU.

	 */

	if (!IS_DGFX(xe)) {

		switch (bo->cpu_caching) {

		case DRM_XE_GEM_CPU_CACHING_WC:

			caching = ttm_write_combined;
@@ -371,12 +378,14 @@ static struct ttm_tt *xe_ttm_tt_create(struct ttm_buffer_object *ttm_bo, 
		/*

		 * Display scanout is always non-coherent with the CPU cache.

		 *

	 * For Xe_LPG and beyond, PPGTT PTE lookups are also non-coherent and

	 * require a CPU:WC mapping.

		 * For Xe_LPG and beyond, PPGTT PTE lookups are also

		 * non-coherent and require a CPU:WC mapping.

		 */

		if ((!bo->cpu_caching && bo->flags & XE_BO_FLAG_SCANOUT) ||

	    (xe->info.graphics_verx100 >= 1270 && bo->flags & XE_BO_FLAG_PAGETABLE))

		    (xe->info.graphics_verx100 >= 1270 &&

		     bo->flags & XE_BO_FLAG_PAGETABLE))

			caching = ttm_write_combined;

	}



	if (bo->flags & XE_BO_FLAG_NEEDS_UC) {

		/*

drivers/gpu/drm/xe/xe_bo_types.h

+2 −1
Original line number Diff line number Diff line
@@ -68,7 +68,8 @@ struct xe_bo { 


	/**

	 * @cpu_caching: CPU caching mode. Currently only used for userspace

	 * objects.

	 * objects. Exceptions are system memory on DGFX, which is always

	 * WB.

	 */

	u16 cpu_caching;

include/uapi/drm/xe_drm.h

+7 −1
Original line number Diff line number Diff line
@@ -783,7 +783,13 @@ struct drm_xe_gem_create { 
#define DRM_XE_GEM_CPU_CACHING_WC                      2

	/**

	 * @cpu_caching: The CPU caching mode to select for this object. If

	 * mmaping the object the mode selected here will also be used.

	 * mmaping the object the mode selected here will also be used. The

	 * exception is when mapping system memory (including data evicted

	 * to system) on discrete GPUs. The caching mode selected will

	 * then be overridden to DRM_XE_GEM_CPU_CACHING_WB, and coherency

	 * between GPU- and CPU is guaranteed. The caching mode of

	 * existing CPU-mappings will be updated transparently to

	 * user-space clients.

	 */

	__u16 cpu_caching;

	/** @pad: MBZ */