Unverified Commit 0229278b authored by Sam Protsenko's avatar Sam Protsenko Committed by Mark Brown
Browse files

spi: s3c64xx: Add Exynos850 support 



Add SPI port configuration for Exynos850 SoC. It has 3 USI blocks which
can be configured in SPI mode:

  * spi_0: BLK_PERI_SPI_0 (0x13940000)
  * spi_1: BLK_ALIVE_USI_CMGP00 (0x11d00000)
  * spi_2: BLK_ALIVE_USI_CMGP01 (0x11d20000)

SPI FIFO depth is 64 bytes for all those SPI blocks, so the
.fifo_lvl_mask value is set to 0x7f. All blocks have DIV_4 as the
default internal clock divider, and an internal loopback mode to run
a loopback test.

Signed-off-by: default avatarSam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: default avatarTudor Ambarus <tudor.ambarus@linaro.org>
Link: https://msgid.link/r/20240120012948.8836-6-semen.protsenko@linaro.org


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 18ab9e9e

drivers/spi/spi-s3c64xx.c

+14 −0
Original line number Diff line number Diff line
@@ -1460,6 +1460,17 @@ static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = { 
	.quirks		= S3C64XX_SPI_QUIRK_CS_AUTO,

};



static const struct s3c64xx_spi_port_config exynos850_spi_port_config = {

	.fifo_lvl_mask	= { 0x7f, 0x7f, 0x7f },

	.rx_lvl_offset	= 15,

	.tx_st_done	= 25,

	.clk_div	= 4,

	.high_speed	= true,

	.clk_from_cmu	= true,

	.has_loopback	= true,

	.quirks		= S3C64XX_SPI_QUIRK_CS_AUTO,

};



static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = {

	.fifo_lvl_mask	= { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f,

			    0x7f, 0x7f, 0x7f, 0x7f},
@@ -1514,6 +1525,9 @@ static const struct of_device_id s3c64xx_spi_dt_match[] = { 
	{ .compatible = "samsung,exynos5433-spi",

			.data = (void *)&exynos5433_spi_port_config,

	},

	{ .compatible = "samsung,exynos850-spi",

			.data = (void *)&exynos850_spi_port_config,

	},

	{ .compatible = "samsung,exynosautov9-spi",

			.data = (void *)&exynosautov9_spi_port_config,

	},