Commit 024771f3 authored Dec 10, 2024 by Aric Cyr Committed by Alex Deucher Jan 24, 2025

drm/amd/display: Optimize cursor position updates



[why]
Updating the cursor enablement register can be a slow operation and accumulates
when high polling rate cursors cause frequent updates asynchronously to the
cursor position.

[how]
Since the cursor enable bit is cached there is no need to update the
enablement register if there is no change to it.  This removes the
read-modify-write from the cursor position programming path in HUBP and
DPP, leaving only the register writes.

Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Reviewed-by: Sung Lee <sung.lee@amd.com>
Signed-off-by: Aric Cyr <Aric.Cyr@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent 01130f52

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

+4 −3

Original line number	Diff line number	Diff line
		@@ -483,11 +483,12 @@ void dpp1_set_cursor_position(
		if (src_y_offset + cursor_height <= 0)
		cur_en = 0; /* not visible beyond top edge*/

		REG_UPDATE(CURSOR0_CONTROL,
		CUR0_ENABLE, cur_en);
		if (dpp_base->pos.cur0_ctl.bits.cur0_enable != cur_en) {
		REG_UPDATE(CURSOR0_CONTROL, CUR0_ENABLE, cur_en);

		dpp_base->pos.cur0_ctl.bits.cur0_enable = cur_en;
		}
		}

		void dpp1_cnv_set_optional_cursor_attributes(
		struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

+4 −2

Original line number	Diff line number	Diff line
		@@ -154,10 +154,12 @@ void dpp401_set_cursor_position(
		struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);
		uint32_t cur_en = pos->enable ? 1 : 0;

		if (dpp_base->pos.cur0_ctl.bits.cur0_enable != cur_en) {
		REG_UPDATE(CURSOR0_CONTROL, CUR0_ENABLE, cur_en);

		dpp_base->pos.cur0_ctl.bits.cur0_enable = cur_en;
		}
		}

		void dpp401_set_optional_cursor_attributes(
		struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

+5 −3

Original line number	Diff line number	Diff line
		@@ -1058,11 +1058,13 @@ void hubp2_cursor_set_position(
		if (src_y_offset + cursor_height <= 0)
		cur_en = 0; /* not visible beyond top edge*/

		if (hubp->pos.cur_ctl.bits.cur_enable != cur_en) {
		if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
		hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);

		REG_UPDATE(CURSOR_CONTROL,
		CURSOR_ENABLE, cur_en);
		}

		REG_SET_2(CURSOR_POSITION, 0,
		CURSOR_X_POSITION, pos->x,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

+6 −4

Original line number	Diff line number	Diff line
		@@ -742,11 +742,13 @@ void hubp401_cursor_set_position(
		dc_fixpt_from_int(dst_x_offset),
		param->h_scale_ratio));

		if (hubp->pos.cur_ctl.bits.cur_enable != cur_en) {
		if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
		hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);

		REG_UPDATE(CURSOR_CONTROL,
		CURSOR_ENABLE, cur_en);
		}

		REG_SET_2(CURSOR_POSITION, 0,
		CURSOR_X_POSITION, x_pos,