Commit 025cce25 authored by Ian Rogers's avatar Ian Rogers Committed by Namhyung Kim
Browse files

perf vendor events: Add knightslanding counter information

Add counter information necessary for optimizing event grouping the
perf tool.

The most recent RFC patch set using this information:
https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/

The information was added in:
https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4765e1


and later patches.

Co-authored-by: default avatarWeilin Wang <weilin.wang@intel.com>
Co-authored-by: default avatarCaleb Biggers <caleb.biggers@intel.com>
Signed-off-by: default avatarIan Rogers <irogers@google.com>
Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: default avatarNamhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/r/20240620181752.3945845-22-irogers@google.com
parent 87916225
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Original line number Diff line number Diff line
[
    {
        "Unit": "core",
        "CountersNumFixed": "3",
        "CountersNumGeneric": "2"
    },
    {
        "Unit": "CHA",
        "CountersNumFixed": "0",
        "CountersNumGeneric": "4"
    },
    {
        "Unit": "EDC_ECLK",
        "CountersNumFixed": "0",
        "CountersNumGeneric": "4"
    },
    {
        "Unit": "EDC_UCLK",
        "CountersNumFixed": "0",
        "CountersNumGeneric": "4"
    },
    {
        "Unit": "iMC_DCLK",
        "CountersNumFixed": "0",
        "CountersNumGeneric": "4"
    },
    {
        "Unit": "iMC_UCLK",
        "CountersNumFixed": "0",
        "CountersNumGeneric": 4
    },
    {
        "Unit": "M2PCIe",
        "CountersNumFixed": "0",
        "CountersNumGeneric": "4"
    }
]
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+3 −0
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[
    {
        "BriefDescription": "Counts the number of floating operations retired that required microcode assists",
        "Counter": "0,1",
        "EventCode": "0xC3",
        "EventName": "MACHINE_CLEARS.FP_ASSIST",
        "PublicDescription": "This event counts the number of times that the pipeline stalled due to FP operations needing assists.",
@@ -9,6 +10,7 @@
    },
    {
        "BriefDescription": "Counts the number of packed SSE, AVX, AVX2, AVX-512 micro-ops (both floating point and integer) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies.",
        "Counter": "0,1",
        "EventCode": "0xC2",
        "EventName": "UOPS_RETIRED.PACKED_SIMD",
        "PublicDescription": "The length of the packed operation (128bits, 256bits or 512bits) is not taken into account when updating the counter; all count the same (+1). \r\nMask (k) registers are ignored. For example: a micro-op operating with a mask that only enables one element or even zero elements will still trigger this counter (+1)\r\nThis event is defined at the micro-op level and not instruction level. Most instructions are implemented with one micro-op but not all.",
@@ -17,6 +19,7 @@
    },
    {
        "BriefDescription": "Counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops except for loads (memory-to-register mov-type micro ops), division, sqrt.",
        "Counter": "0,1",
        "EventCode": "0xC2",
        "EventName": "UOPS_RETIRED.SCALAR_SIMD",
        "PublicDescription": "This event is defined at the micro-op level and not instruction level. Most instructions are implemented with one micro-op but not all.",
+7 −0
Original line number Diff line number Diff line
[
    {
        "BriefDescription": "Counts the number of times the front end resteers for any branch as a result of another branch handling mechanism in the front end.",
        "Counter": "0,1",
        "EventCode": "0xE6",
        "EventName": "BACLEARS.ALL",
        "SampleAfterValue": "200003",
@@ -8,6 +9,7 @@
    },
    {
        "BriefDescription": "Counts the number of times the front end resteers for conditional branches as a result of another branch handling mechanism in the front end.",
        "Counter": "0,1",
        "EventCode": "0xE6",
        "EventName": "BACLEARS.COND",
        "SampleAfterValue": "200003",
@@ -15,6 +17,7 @@
    },
    {
        "BriefDescription": "Counts the number of times the front end resteers for RET branches as a result of another branch handling mechanism in the front end.",
        "Counter": "0,1",
        "EventCode": "0xE6",
        "EventName": "BACLEARS.RETURN",
        "SampleAfterValue": "200003",
@@ -22,6 +25,7 @@
    },
    {
        "BriefDescription": "Counts all instruction fetches, including uncacheable fetches.",
        "Counter": "0,1",
        "EventCode": "0x80",
        "EventName": "ICACHE.ACCESSES",
        "SampleAfterValue": "200003",
@@ -29,6 +33,7 @@
    },
    {
        "BriefDescription": "Counts all instruction fetches that hit the instruction cache.",
        "Counter": "0,1",
        "EventCode": "0x80",
        "EventName": "ICACHE.HIT",
        "SampleAfterValue": "200003",
@@ -36,6 +41,7 @@
    },
    {
        "BriefDescription": "Counts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstanding.",
        "Counter": "0,1",
        "EventCode": "0x80",
        "EventName": "ICACHE.MISSES",
        "SampleAfterValue": "200003",
@@ -43,6 +49,7 @@
    },
    {
        "BriefDescription": "Counts the number of times the MSROM starts a flow of uops.",
        "Counter": "0,1",
        "EventCode": "0xE7",
        "EventName": "MS_DECODED.MS_ENTRY",
        "SampleAfterValue": "200003",
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