Commit 02a2793a authored by Patel, Swapnil's avatar Patel, Swapnil Committed by Alex Deucher
Browse files

drm/amd/display: Refactor DCN4x and related code 



[why & how]
Refactor existing code related to DCN4x for better code sharing with
other modules.

Reviewed-by: default avatarCharlene Liu <charlene.liu@amd.com>
Signed-off-by: default avatarSwapnil Patel <Swapnil.Patel@amd.com>
Signed-off-by: default avatarZaeem Mohamed <zaeem.mohamed@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f6d17270

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

+48 −46
Original line number Diff line number Diff line
@@ -379,53 +379,55 @@ struct dccg_mask { 
	DCCG401_REG_FIELD_LIST(uint32_t)

};



#define DCCG_REG_VARIABLE_LIST \

	uint32_t DPPCLK_DTO_CTRL; \

	uint32_t DPPCLK_DTO_PARAM[6]; \

	uint32_t REFCLK_CNTL; \

	uint32_t DISPCLK_FREQ_CHANGE_CNTL; \

	uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES]; \

	uint32_t HDMICHARCLK_CLOCK_CNTL[6]; \

	uint32_t PHYASYMCLK_CLOCK_CNTL; \

	uint32_t PHYBSYMCLK_CLOCK_CNTL; \

	uint32_t PHYCSYMCLK_CLOCK_CNTL; \

	uint32_t PHYDSYMCLK_CLOCK_CNTL; \

	uint32_t PHYESYMCLK_CLOCK_CNTL; \

	uint32_t DTBCLK_DTO_MODULO[MAX_PIPES]; \

	uint32_t DTBCLK_DTO_PHASE[MAX_PIPES]; \

	uint32_t DCCG_AUDIO_DTBCLK_DTO_MODULO; \

	uint32_t DCCG_AUDIO_DTBCLK_DTO_PHASE; \

	uint32_t DCCG_AUDIO_DTO_SOURCE; \

	uint32_t DPSTREAMCLK_CNTL; \

	uint32_t HDMISTREAMCLK_CNTL; \

	uint32_t SYMCLK32_SE_CNTL; \

	uint32_t SYMCLK32_LE_CNTL; \

	uint32_t DENTIST_DISPCLK_CNTL; \

	uint32_t DSCCLK_DTO_CTRL; \

	uint32_t DSCCLK0_DTO_PARAM; \

	uint32_t DSCCLK1_DTO_PARAM; \

	uint32_t DSCCLK2_DTO_PARAM; \

	uint32_t DSCCLK3_DTO_PARAM; \

	uint32_t DPSTREAMCLK_ROOT_GATE_DISABLE; \

	uint32_t DPSTREAMCLK_GATE_DISABLE; \

	uint32_t DCCG_GATE_DISABLE_CNTL; \

	uint32_t DCCG_GATE_DISABLE_CNTL2; \

	uint32_t DCCG_GATE_DISABLE_CNTL3; \

	uint32_t HDMISTREAMCLK0_DTO_PARAM; \

	uint32_t DCCG_GATE_DISABLE_CNTL4; \

	uint32_t OTG_PIXEL_RATE_DIV; \

	uint32_t DTBCLK_P_CNTL; \

	uint32_t DPPCLK_CTRL; \

	uint32_t DCCG_GATE_DISABLE_CNTL5; \

	uint32_t DCCG_GATE_DISABLE_CNTL6; \

	uint32_t DCCG_GLOBAL_FGCG_REP_CNTL; \

	uint32_t SYMCLKA_CLOCK_ENABLE; \

	uint32_t SYMCLKB_CLOCK_ENABLE; \

	uint32_t SYMCLKC_CLOCK_ENABLE; \

	uint32_t SYMCLKD_CLOCK_ENABLE; \

	uint32_t SYMCLKE_CLOCK_ENABLE; \

	uint32_t DP_DTO_MODULO[MAX_PIPES]; \

	uint32_t DP_DTO_PHASE[MAX_PIPES]

struct dccg_registers {

	uint32_t DPPCLK_DTO_CTRL;

	uint32_t DPPCLK_DTO_PARAM[6];

	uint32_t REFCLK_CNTL;

	uint32_t DISPCLK_FREQ_CHANGE_CNTL;

	uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES];

	uint32_t HDMICHARCLK_CLOCK_CNTL[6];

	uint32_t PHYASYMCLK_CLOCK_CNTL;

	uint32_t PHYBSYMCLK_CLOCK_CNTL;

	uint32_t PHYCSYMCLK_CLOCK_CNTL;

	uint32_t PHYDSYMCLK_CLOCK_CNTL;

	uint32_t PHYESYMCLK_CLOCK_CNTL;

	uint32_t DTBCLK_DTO_MODULO[MAX_PIPES];

	uint32_t DTBCLK_DTO_PHASE[MAX_PIPES];

	uint32_t DCCG_AUDIO_DTBCLK_DTO_MODULO;

	uint32_t DCCG_AUDIO_DTBCLK_DTO_PHASE;

	uint32_t DCCG_AUDIO_DTO_SOURCE;

	uint32_t DPSTREAMCLK_CNTL;

	uint32_t HDMISTREAMCLK_CNTL;

	uint32_t SYMCLK32_SE_CNTL;

	uint32_t SYMCLK32_LE_CNTL;

	uint32_t DENTIST_DISPCLK_CNTL;

	uint32_t DSCCLK_DTO_CTRL;

	uint32_t DSCCLK0_DTO_PARAM;

	uint32_t DSCCLK1_DTO_PARAM;

	uint32_t DSCCLK2_DTO_PARAM;

	uint32_t DSCCLK3_DTO_PARAM;

	uint32_t DPSTREAMCLK_ROOT_GATE_DISABLE;

	uint32_t DPSTREAMCLK_GATE_DISABLE;

	uint32_t DCCG_GATE_DISABLE_CNTL;

	uint32_t DCCG_GATE_DISABLE_CNTL2;

	uint32_t DCCG_GATE_DISABLE_CNTL3;

	uint32_t HDMISTREAMCLK0_DTO_PARAM;

	uint32_t DCCG_GATE_DISABLE_CNTL4;

	uint32_t OTG_PIXEL_RATE_DIV;

	uint32_t DTBCLK_P_CNTL;

	uint32_t DPPCLK_CTRL;

	uint32_t DCCG_GATE_DISABLE_CNTL5;

	uint32_t DCCG_GATE_DISABLE_CNTL6;

	uint32_t DCCG_GLOBAL_FGCG_REP_CNTL;

	uint32_t SYMCLKA_CLOCK_ENABLE;

	uint32_t SYMCLKB_CLOCK_ENABLE;

	uint32_t SYMCLKC_CLOCK_ENABLE;

	uint32_t SYMCLKD_CLOCK_ENABLE;

	uint32_t SYMCLKE_CLOCK_ENABLE;

	uint32_t DP_DTO_MODULO[MAX_PIPES];

	uint32_t DP_DTO_PHASE[MAX_PIPES];

	DCCG_REG_VARIABLE_LIST;

};



struct dcn_dccg {

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

+1 −1
Original line number Diff line number Diff line
@@ -531,7 +531,7 @@ static void dccg401_enable_dpstreamclk(struct dccg *dccg, int otg_inst, int dp_h 
			DPSTREAMCLK_ROOT_GATE_DISABLE, 1);

}



static void dccg401_disable_dpstreamclk(struct dccg *dccg, int dp_hpo_inst)

void dccg401_disable_dpstreamclk(struct dccg *dccg, int dp_hpo_inst)

{

	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

+2 −3
Original line number Diff line number Diff line
@@ -208,6 +208,8 @@ void dccg401_enable_symclk32_le( 
void dccg401_disable_symclk32_le(

		struct dccg *dccg,

		int hpo_le_inst);

void dccg401_disable_dpstreamclk(struct dccg *dccg, int dp_hpo_inst);

void dccg401_set_dto_dscclk(struct dccg *dccg, uint32_t inst);

void dccg401_set_ref_dscclk(struct dccg *dccg,

				uint32_t dsc_inst);

void dccg401_set_src_sel(
@@ -228,14 +230,11 @@ void dccg401_set_dp_dto( 
		const struct dp_dto_params *params);

void dccg401_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst);

void dccg401_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst);



void dccg401_set_dto_dscclk(struct dccg *dccg, uint32_t inst);

void dccg401_set_dtbclk_p_src(

		struct dccg *dccg,

		enum streamclk_source src,

		uint32_t otg_inst);





struct dccg *dccg401_create(

	struct dc_context *ctx,

	const struct dccg_registers *regs,

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

+1 −1
Original line number Diff line number Diff line
@@ -100,7 +100,7 @@ void enc401_stream_encoder_dvi_set_stream_attribute( 
}



/* setup stream encoder in hdmi mode */

static void enc401_stream_encoder_hdmi_set_stream_attribute(

void enc401_stream_encoder_hdmi_set_stream_attribute(

	struct stream_encoder *enc,

	struct dc_crtc_timing *crtc_timing,

	int actual_pix_clk_khz,

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.h

+5 −0
Original line number Diff line number Diff line
@@ -232,4 +232,9 @@ void enc401_stream_encoder_map_to_link( 
		uint32_t stream_enc_inst,

		uint32_t link_enc_inst);

void enc401_read_state(struct stream_encoder *enc, struct enc_state *s);

void enc401_stream_encoder_hdmi_set_stream_attribute(

	struct stream_encoder *enc,

	struct dc_crtc_timing *crtc_timing,

	int actual_pix_clk_khz,

	bool enable_audio);

#endif /* __DC_DIO_STREAM_ENCODER_DCN401_H__ */