Commit 02c13216 authored by David Belanger's avatar David Belanger Committed by Alex Deucher
Browse files

drm/amdkfd: Add cache line size info 



Populate cache line size info in topology based on information from IP
discovery table.

Signed-off-by: default avatarDavid Belanger <david.belanger@amd.com>
Reviewed-by: default avatarSreekant Somasekharan <Sreekant.Somasekharan@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 4e9fadac)
parent 141bb6bc

drivers/gpu/drm/amd/amdkfd/kfd_crat.c

+7 −1
Original line number Diff line number Diff line
@@ -1434,7 +1434,8 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev, 
		pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |

					CRAT_CACHE_FLAGS_DATA_CACHE |

					CRAT_CACHE_FLAGS_SIMD_CACHE);

		pcache_info[0].num_cu_shared = adev->gfx.config.gc_num_tcp_per_wpg / 2;

		pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_tcp_per_wpg / 2;

		pcache_info[i].cache_line_size = adev->gfx.config.gc_tcp_cache_line_size;

		i++;

	}

	/* Scalar L1 Instruction Cache per SQC */
@@ -1446,6 +1447,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev, 
					CRAT_CACHE_FLAGS_INST_CACHE |

					CRAT_CACHE_FLAGS_SIMD_CACHE);

		pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_sqc_per_wgp * 2;

		pcache_info[i].cache_line_size = adev->gfx.config.gc_instruction_cache_line_size;

		i++;

	}

	/* Scalar L1 Data Cache per SQC */
@@ -1456,6 +1458,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev, 
					CRAT_CACHE_FLAGS_DATA_CACHE |

					CRAT_CACHE_FLAGS_SIMD_CACHE);

		pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_sqc_per_wgp * 2;

		pcache_info[i].cache_line_size = adev->gfx.config.gc_scalar_data_cache_line_size;

		i++;

	}

	/* GL1 Data Cache per SA */
@@ -1468,6 +1471,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev, 
					CRAT_CACHE_FLAGS_DATA_CACHE |

					CRAT_CACHE_FLAGS_SIMD_CACHE);

		pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;

		pcache_info[i].cache_line_size = 0;

		i++;

	}

	/* L2 Data Cache per GPU (Total Tex Cache) */
@@ -1478,6 +1482,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev, 
					CRAT_CACHE_FLAGS_DATA_CACHE |

					CRAT_CACHE_FLAGS_SIMD_CACHE);

		pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;

		pcache_info[i].cache_line_size = adev->gfx.config.gc_tcc_cache_line_size;

		i++;

	}

	/* L3 Data Cache per GPU */
@@ -1488,6 +1493,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev, 
					CRAT_CACHE_FLAGS_DATA_CACHE |

					CRAT_CACHE_FLAGS_SIMD_CACHE);

		pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;

		pcache_info[i].cache_line_size = 0;

		i++;

	}

	return i;