Commit 02c4e64a authored by Shekhar Chauhan's avatar Shekhar Chauhan Committed by Matt Roper
Browse files

drm/xe/xe2_lpg: Introduce performance guide changes 



Add performance guide changes to Xe2_LPG.

BSpec: 72161
Signed-off-by: default avatarShekhar Chauhan <shekhar.chauhan@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240123050552.2250699-2-shekhar.chauhan@intel.com
parent c885886b

drivers/gpu/drm/xe/regs/xe_gt_regs.h

+6 −0
Original line number Diff line number Diff line
@@ -144,6 +144,9 @@ 


#define GSCPSMI_BASE				XE_REG(0x880c)



#define CCCHKNREG1				XE_REG_MCR(0x8828)

#define   ENCOMPPERFFIX				REG_BIT(18)



/* Fuse readout registers for GT */

#define XEHP_FUSE4				XE_REG(0x9114)

#define   CFEG_WMTP_DISABLE			REG_BIT(20)
@@ -289,6 +292,9 @@ 
#define XEHP_L3NODEARBCFG			XE_REG_MCR(0xb0b4)

#define   XEHP_LNESPARE				REG_BIT(19)



#define L3SQCREG3				XE_REG_MCR(0xb108)

#define   COMPPWOVERFETCHEN			REG_BIT(28)



#define XEHP_L3SQCREG5				XE_REG_MCR(0xb158)

#define   L3_PWM_TIMER_INIT_VAL_MASK		REG_GENMASK(9, 0)

drivers/gpu/drm/xe/xe_tuning.c

+8 −1
Original line number Diff line number Diff line
@@ -37,7 +37,14 @@ static const struct xe_rtp_entry_sr gt_tunings[] = { 
	  XE_RTP_ACTIONS(FIELD_SET(XE2LPM_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,

				   REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))

	},



	{ XE_RTP_NAME("Tuning: Compression Overfetch"),

	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2004, XE_RTP_END_VERSION_UNDEFINED)),

	  XE_RTP_ACTIONS(CLR(CCCHKNREG1, ENCOMPPERFFIX)),

	},

	{ XE_RTP_NAME("Tuning: Enable compressible partial write overfetch in L3"),

	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2004, XE_RTP_END_VERSION_UNDEFINED)),

	  XE_RTP_ACTIONS(SET(L3SQCREG3, COMPPWOVERFETCHEN))

	},

	{}

};