Commit 02fb638b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm 

Pull ARM updates from Russell King:

 - remove a misuse of kernel-doc comment

 - use "Call trace:" for backtraces like other architectures

 - implement copy_from_kernel_nofault_allowed() to fix a LKDTM test

 - add a "cut here" line for prefetch aborts

 - remove unnecessary Kconfing entry for FRAME_POINTER

 - remove iwmmxy support for PJ4/PJ4B cores

 - use bitfield helpers in ptrace to improve readabililty

 - check if folio is reserved before flushing

* tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm:
  ARM: 9359/1: flush: check if the folio is reserved for no-mapping addresses
  ARM: 9354/1: ptrace: Use bitfield helpers
  ARM: 9352/1: iwmmxt: Remove support for PJ4/PJ4B cores
  ARM: 9353/1: remove unneeded entry for CONFIG_FRAME_POINTER
  ARM: 9351/1: fault: Add "cut here" line for prefetch aborts
  ARM: 9350/1: fault: Implement copy_from_kernel_nofault_allowed()
  ARM: 9349/1: unwind: Add missing "Call trace:" line
  ARM: 9334/1: mm: init: remove misuse of kernel-doc comment
parents b7187139 b42b3ae1

arch/arm/Kconfig

+2 −2
Original line number Diff line number Diff line
@@ -505,8 +505,8 @@ source "arch/arm/mm/Kconfig" 


config IWMMXT

	bool "Enable iWMMXt support"

	depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B

	default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B

	depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK

	default y if PXA27x || PXA3xx || ARCH_MMP

	help

	  Enable support for iWMMXt context switching at run time if

	  running on a CPU that supports it.

arch/arm/Kconfig.debug

+0 −3
Original line number Diff line number Diff line
@@ -90,9 +90,6 @@ config BACKTRACE_VERBOSE 
	  In most cases, say N here, unless you are intending to debug the

	  kernel and have access to the kernel binary image.



config FRAME_POINTER

	bool



config DEBUG_USER

	bool "Verbose user fault messages"

	help

arch/arm/include/asm/ptrace.h

+3 −2
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ 
#include <uapi/asm/ptrace.h>



#ifndef __ASSEMBLY__

#include <linux/bitfield.h>

#include <linux/types.h>



struct pt_regs {
@@ -35,8 +36,8 @@ struct svc_pt_regs { 


#ifndef CONFIG_CPU_V7M

#define isa_mode(regs) \

	((((regs)->ARM_cpsr & PSR_J_BIT) >> (__ffs(PSR_J_BIT) - 1)) | \

	 (((regs)->ARM_cpsr & PSR_T_BIT) >> (__ffs(PSR_T_BIT))))

	(FIELD_GET(PSR_J_BIT, (regs)->ARM_cpsr) << 1 | \

	 FIELD_GET(PSR_T_BIT, (regs)->ARM_cpsr))

#else

#define isa_mode(regs) 1 /* Thumb */

#endif

arch/arm/kernel/Makefile

+0 −2
Original line number Diff line number Diff line
@@ -76,8 +76,6 @@ obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o 
obj-$(CONFIG_CPU_XSCALE)	+= xscale-cp0.o

obj-$(CONFIG_CPU_XSC3)		+= xscale-cp0.o

obj-$(CONFIG_CPU_MOHAWK)	+= xscale-cp0.o

obj-$(CONFIG_CPU_PJ4)		+= pj4-cp0.o

obj-$(CONFIG_CPU_PJ4B)		+= pj4-cp0.o

obj-$(CONFIG_IWMMXT)		+= iwmmxt.o

obj-$(CONFIG_PERF_EVENTS)	+= perf_regs.o perf_callchain.o

obj-$(CONFIG_HW_PERF_EVENTS)	+= perf_event_xscale.o perf_event_v6.o \

arch/arm/kernel/iwmmxt.S

+13 −38
Original line number Diff line number Diff line
@@ -18,18 +18,6 @@ 
#include <asm/assembler.h>

#include "iwmmxt.h"



#if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)

#define PJ4(code...)		code

#define XSC(code...)

#elif defined(CONFIG_CPU_MOHAWK) || \

	defined(CONFIG_CPU_XSC3) || \

	defined(CONFIG_CPU_XSCALE)

#define PJ4(code...)

#define XSC(code...)		code

#else

#error "Unsupported iWMMXt architecture"

#endif



#define MMX_WR0		 	(0x00)

#define MMX_WR1		 	(0x08)

#define MMX_WR2		 	(0x10)
@@ -81,17 +69,13 @@ ENDPROC(iwmmxt_undef_handler) 
ENTRY(iwmmxt_task_enable)

	inc_preempt_count r10, r3



	XSC(mrc	p15, 0, r2, c15, c1, 0)

	PJ4(mrc p15, 0, r2, c1, c0, 2)

	mrc	p15, 0, r2, c15, c1, 0

	@ CP0 and CP1 accessible?

	XSC(tst	r2, #0x3)

	PJ4(tst	r2, #0xf)

	tst	r2, #0x3

	bne	4f				@ if so no business here

	@ enable access to CP0 and CP1

	XSC(orr	r2, r2, #0x3)

	XSC(mcr	p15, 0, r2, c15, c1, 0)

	PJ4(orr	r2, r2, #0xf)

	PJ4(mcr	p15, 0, r2, c1, c0, 2)

	orr	r2, r2, #0x3

	mcr	p15, 0, r2, c15, c1, 0



	ldr	r3, =concan_owner

	ldr	r2, [r0, #S_PC]			@ current task pc value
@@ -218,12 +202,9 @@ ENTRY(iwmmxt_task_disable) 
	bne	1f				@ no: quit



	@ enable access to CP0 and CP1

	XSC(mrc	p15, 0, r4, c15, c1, 0)

	XSC(orr	r4, r4, #0x3)

	XSC(mcr	p15, 0, r4, c15, c1, 0)

	PJ4(mrc p15, 0, r4, c1, c0, 2)

	PJ4(orr	r4, r4, #0xf)

	PJ4(mcr	p15, 0, r4, c1, c0, 2)

	mrc	p15, 0, r4, c15, c1, 0

	orr	r4, r4, #0x3

	mcr	p15, 0, r4, c15, c1, 0



	mov	r0, #0				@ nothing to load

	str	r0, [r3]			@ no more current owner
@@ -232,10 +213,8 @@ ENTRY(iwmmxt_task_disable) 
	bl	concan_save



	@ disable access to CP0 and CP1

	XSC(bic	r4, r4, #0x3)

	XSC(mcr	p15, 0, r4, c15, c1, 0)

	PJ4(bic	r4, r4, #0xf)

	PJ4(mcr	p15, 0, r4, c1, c0, 2)

	bic	r4, r4, #0x3

	mcr	p15, 0, r4, c15, c1, 0



	mrc	p15, 0, r2, c2, c0, 0

	mov	r2, r2				@ cpwait
@@ -330,11 +309,9 @@ ENDPROC(iwmmxt_task_restore) 
 */

ENTRY(iwmmxt_task_switch)



	XSC(mrc	p15, 0, r1, c15, c1, 0)

	PJ4(mrc	p15, 0, r1, c1, c0, 2)

	mrc	p15, 0, r1, c15, c1, 0

	@ CP0 and CP1 accessible?

	XSC(tst	r1, #0x3)

	PJ4(tst	r1, #0xf)

	tst	r1, #0x3

	bne	1f				@ yes: block them for next task



	ldr	r2, =concan_owner
@@ -344,10 +321,8 @@ ENTRY(iwmmxt_task_switch) 
	retne	lr				@ no: leave Concan disabled



1:	@ flip Concan access

	XSC(eor	r1, r1, #0x3)

	XSC(mcr	p15, 0, r1, c15, c1, 0)

	PJ4(eor r1, r1, #0xf)

	PJ4(mcr	p15, 0, r1, c1, c0, 2)

	eor	r1, r1, #0x3

	mcr	p15, 0, r1, c15, c1, 0



	mrc	p15, 0, r1, c2, c0, 0

	sub	pc, lr, r1, lsr #32		@ cpwait and return