Commit 03713108 authored by Carolina Jubran's avatar Carolina Jubran Committed by Leon Romanovsky
Browse files

net/mlx5: Add support for new scheduling elements 



Introduce new scheduling elements in the E-Switch QoS hierarchy to
enhance traffic management capabilities. This patch adds support for:

- Rate Limit scheduling elements: Enables bandwidth limitation across
  multiple nodes without a shared ancestor, providing a mechanism for
  more granular control of bandwidth allocation.

- Traffic Class Transmit Scheduling Arbiter (TSAR): Introduces the
  infrastructure for creating Traffic Class TSARs, allowing
  hierarchical arbitration based on traffic classes.

- Traffic Class Arbiter TSAR: Adds support for a TSAR capable of
  managing arbitration between multiple traffic classes, enabling
  improved bandwidth prioritization and traffic management.

No functional changes are introduced in this patch.

Signed-off-by: default avatarCarolina Jubran <cjubran@nvidia.com>
Reviewed-by: default avatarCosmin Ratiu <cratiu@nvidia.com>
Signed-off-by: default avatarTariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/20241204220931.254964-4-tariqt@nvidia.com


Signed-off-by: default avatarLeon Romanovsky <leon@kernel.org>
parent e799ac9d

drivers/net/ethernet/mellanox/mlx5/core/rl.c

+4 −0
Original line number Diff line number Diff line
@@ -56,6 +56,8 @@ bool mlx5_qos_tsar_type_supported(struct mlx5_core_dev *dev, int type, u8 hierar 
		return cap & TSAR_TYPE_CAP_MASK_ROUND_ROBIN;

	case TSAR_ELEMENT_TSAR_TYPE_ETS:

		return cap & TSAR_TYPE_CAP_MASK_ETS;

	case TSAR_ELEMENT_TSAR_TYPE_TC_ARB:

		return cap & TSAR_TYPE_CAP_MASK_TC_ARB;

	}



	return false;
@@ -87,6 +89,8 @@ bool mlx5_qos_element_type_supported(struct mlx5_core_dev *dev, int type, u8 hie 
		return cap & ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC;

	case SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP:

		return cap & ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP;

	case SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT:

		return cap & ELEMENT_TYPE_CAP_MASK_RATE_LIMIT;

	}



	return false;

include/linux/mlx5/mlx5_ifc.h

+11 −3
Original line number Diff line number Diff line
@@ -1103,7 +1103,8 @@ struct mlx5_ifc_qos_cap_bits { 


	u8         packet_pacing_min_rate[0x20];



	u8         reserved_at_80[0x10];

	u8         reserved_at_80[0xb];

	u8         log_esw_max_rate_limit[0x5];

	u8         packet_pacing_rate_table_size[0x10];



	u8         esw_element_type[0x10];
@@ -4104,6 +4105,7 @@ enum { 
	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,

	SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,

	SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,

	SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT = 0x5,

};



enum {
@@ -4112,22 +4114,26 @@ enum { 
	ELEMENT_TYPE_CAP_MASK_VPORT_TC		= 1 << 2,

	ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC	= 1 << 3,

	ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP	= 1 << 4,

	ELEMENT_TYPE_CAP_MASK_RATE_LIMIT	= 1 << 5,

};



enum {

	TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,

	TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,

	TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,

	TSAR_ELEMENT_TSAR_TYPE_TC_ARB = 0x3,

};



enum {

	TSAR_TYPE_CAP_MASK_DWRR		= 1 << 0,

	TSAR_TYPE_CAP_MASK_ROUND_ROBIN	= 1 << 1,

	TSAR_TYPE_CAP_MASK_ETS		= 1 << 2,

	TSAR_TYPE_CAP_MASK_TC_ARB       = 1 << 3,

};



struct mlx5_ifc_tsar_element_bits {

	u8         reserved_at_0[0x8];

	u8         traffic_class[0x4];

	u8         reserved_at_4[0x4];

	u8         tsar_type[0x8];

	u8         reserved_at_10[0x10];

};
@@ -4164,7 +4170,9 @@ struct mlx5_ifc_scheduling_context_bits { 


	u8         max_average_bw[0x20];



	u8         reserved_at_e0[0x120];

	u8         max_bw_obj_id[0x20];



	u8         reserved_at_100[0x100];

};



struct mlx5_ifc_rqtc_bits {