Commit 03a53e09 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'irq-drivers-2025-09-29' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull irq chip driver updates from Thomas Gleixner:

 - Use the startup/shutdown callbacks for the PCI/MSI per device
   interrupt domains.

   This allows us to initialize the RISCV PLIC interrupt hierarchy
   correctly and provides a mechanism to decouple the masking and
   unmasking during run-time from the expensive PCI mask and unmask when
   the underlying MSI provider implementation allows the interrupt to be
   masked.

 - Initialize the RISCV PLIC MSI interrupt hierarchy correctly so that
   the affinity assignment works correctly by switching it over to the
   startup/shutdown scheme

 - Allow MSI providers to opt out from masking a PCI/MSI interrupt at
   the PCI device during operation when the provider can mask the
   interrupt at the underlying interrupt chip. This reduces the overhead
   in scenarios where disable_irq()/enable_irq() is utilized frequently
   by a driver.

   The PCI/MSI device level [un]masking is only required on startup and
   shutdown in this case.

 - Remove the conditional mask/unmask logic in the PCI/MSI layer as this
   is now handled unconditionally.

 - Replace the hardcoded interrupt routing in the Loongson EIOINTC
   interrupt driver to respect the firmware settings and spread them out
   to different CPU interrupt inputs so that the demultiplexing handler
   only needs to read only a single 64-bit status register instead of
   four, which significantly reduces the overhead in VMs as the status
   register access causes a VM exit.

 - Add support for the new AST2700 SCU interrupt controllers

 - Use the legacy interrupt domain setup for the Loongson PCH-LPC
   interrupt controller, which resembles the x86 legacy PIC setup and
   has the same hardcoded legacy requirements.

 - The usual set of cleanups, fixes and improvements all over the place

* tag 'irq-drivers-2025-09-29' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (25 commits)
  irqchip/loongson-pch-lpc: Use legacy domain for PCH-LPC IRQ controller
  PCI/MSI: Remove the conditional parent [un]mask logic
  irqchip/msi-lib: Honor the MSI_FLAG_PCI_MSI_MASK_PARENT flag
  irqchip/aspeed-scu-ic: Add support for AST2700 SCU interrupt controllers
  dt-bindings: interrupt-controller: aspeed: Add AST2700 SCU IC compatibles
  dt-bindings: mfd: aspeed: Add AST2700 SCU compatibles
  irqchip/aspeed-scu-ic: Refactor driver to support variant-based initialization
  irqchip/gic-v5: Fix error handling in gicv5_its_irq_domain_alloc()
  irqchip/gic-v5: Fix loop in gicv5_its_create_itt_two_level() cleanup path
  irqchip/gic-v5: Delete a stray tab
  irqchip/sg2042-msi: Set irq type according to DT configuration
  riscv: sophgo: dts: sg2044: Change msi irq type to IRQ_TYPE_EDGE_RISING
  riscv: sophgo: dts: sg2042: Change msi irq type to IRQ_TYPE_EDGE_RISING
  irqchip/gic-v2m: Handle Multiple MSI base IRQ Alignment
  irqchip/renesas-rzg2l: Remove dev_err_probe() if error is -ENOMEM
  irqchip: Use int type to store negative error codes
  irqchip/gic-v5: Remove the redundant ITS cache invalidation
  PCI/MSI: Check MSI_FLAG_PCI_MSI_MASK_PARENT in cond_[startup|shutdown]_parent()
  irqchip/loongson-eiointc: Add multiple interrupt pin routing support
  irqchip/loongson-eiointc: Route interrupt parsed from bios table
  ...
parents 3b2074c7 c33c43f7

Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2500-scu-ic.yaml

+5 −1
Original line number Diff line number Diff line
@@ -5,7 +5,7 @@ 
$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2500-scu-ic.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Aspeed AST25XX and AST26XX SCU Interrupt Controller

title: Aspeed AST25XX, AST26XX, AST27XX SCU Interrupt Controller



maintainers:

  - Eddie James <eajames@linux.ibm.com>
@@ -16,6 +16,10 @@ properties: 
      - aspeed,ast2500-scu-ic

      - aspeed,ast2600-scu-ic0

      - aspeed,ast2600-scu-ic1

      - aspeed,ast2700-scu-ic0

      - aspeed,ast2700-scu-ic1

      - aspeed,ast2700-scu-ic2

      - aspeed,ast2700-scu-ic3



  reg:

    maxItems: 1

Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml

+4 −0
Original line number Diff line number Diff line
@@ -75,6 +75,10 @@ patternProperties: 
            - aspeed,ast2500-scu-ic

            - aspeed,ast2600-scu-ic0

            - aspeed,ast2600-scu-ic1

            - aspeed,ast2700-scu-ic0

            - aspeed,ast2700-scu-ic1

            - aspeed,ast2700-scu-ic2

            - aspeed,ast2700-scu-ic3



  '^silicon-id@[0-9a-f]+$':

    description: Unique hardware silicon identifiers within the SoC

arch/riscv/boot/dts/sophgo/sg2042.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -190,7 +190,7 @@ msi: msi-controller@7030010304 { 
			reg-names = "clr", "doorbell";

			msi-controller;

			#msi-cells = <0>;

			msi-ranges = <&intc 64 IRQ_TYPE_LEVEL_HIGH 32>;

			msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 32>;

		};



		rpgate: clock-controller@7030010368 {

arch/riscv/boot/dts/sophgo/sg2044.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -214,7 +214,7 @@ msi: msi-controller@6d50000000 { 
			reg-names = "clr", "doorbell";

			#msi-cells = <0>;

			msi-controller;

			msi-ranges = <&intc 352 IRQ_TYPE_LEVEL_HIGH 512>;

			msi-ranges = <&intc 352 IRQ_TYPE_EDGE_RISING 512>;

			status = "disabled";

		};

drivers/irqchip/irq-aspeed-scu-ic.c

+155 −101
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-or-later

/*

 * Aspeed AST24XX, AST25XX, and AST26XX SCU Interrupt Controller

 * Aspeed AST24XX, AST25XX, AST26XX, and AST27XX SCU Interrupt Controller

 * Copyright 2019 IBM Corporation

 *

 * Eddie James <eajames@linux.ibm.com>

 */



#include <linux/bitops.h>

#include <linux/io.h>

#include <linux/irq.h>

#include <linux/irqchip.h>

#include <linux/irqchip/chained_irq.h>

#include <linux/irqdomain.h>

#include <linux/mfd/syscon.h>

#include <linux/of_address.h>

#include <linux/of_irq.h>

#include <linux/regmap.h>



#define ASPEED_SCU_IC_REG		0x018

#define ASPEED_SCU_IC_SHIFT		0

#define ASPEED_SCU_IC_ENABLE		GENMASK(15, ASPEED_SCU_IC_SHIFT)

#define ASPEED_SCU_IC_NUM_IRQS		7

#define ASPEED_SCU_IC_STATUS		GENMASK(28, 16)

#define ASPEED_SCU_IC_STATUS_SHIFT	16

#define AST2700_SCU_IC_STATUS		GENMASK(15, 0)



#define ASPEED_AST2600_SCU_IC0_REG	0x560

#define ASPEED_AST2600_SCU_IC0_SHIFT	0

#define ASPEED_AST2600_SCU_IC0_ENABLE	\

	GENMASK(5, ASPEED_AST2600_SCU_IC0_SHIFT)

#define ASPEED_AST2600_SCU_IC0_NUM_IRQS	6

struct aspeed_scu_ic_variant {

	const char	*compatible;

	unsigned long	irq_enable;

	unsigned long	irq_shift;

	unsigned int	num_irqs;

	unsigned long	ier;

	unsigned long	isr;

};



#define ASPEED_AST2600_SCU_IC1_REG	0x570

#define ASPEED_AST2600_SCU_IC1_SHIFT	4

#define ASPEED_AST2600_SCU_IC1_ENABLE	\

	GENMASK(5, ASPEED_AST2600_SCU_IC1_SHIFT)

#define ASPEED_AST2600_SCU_IC1_NUM_IRQS	2

#define SCU_VARIANT(_compat, _shift, _enable, _num, _ier, _isr) {	\

	.compatible		=	_compat,	\

	.irq_shift		=	_shift,		\

	.irq_enable		=	_enable,	\

	.num_irqs		=	_num,		\

	.ier			=	_ier,		\

	.isr			=	_isr,		\

}



static const struct aspeed_scu_ic_variant scu_ic_variants[]	__initconst = {

	SCU_VARIANT("aspeed,ast2400-scu-ic",	0, GENMASK(15, 0),	7, 0x00, 0x00),

	SCU_VARIANT("aspeed,ast2500-scu-ic",	0, GENMASK(15, 0),	7, 0x00, 0x00),

	SCU_VARIANT("aspeed,ast2600-scu-ic0",	0, GENMASK(5, 0),	6, 0x00, 0x00),

	SCU_VARIANT("aspeed,ast2600-scu-ic1",	4, GENMASK(5, 4),	2, 0x00, 0x00),

	SCU_VARIANT("aspeed,ast2700-scu-ic0",	0, GENMASK(3, 0),	4, 0x00, 0x04),

	SCU_VARIANT("aspeed,ast2700-scu-ic1",	0, GENMASK(3, 0),	4, 0x00, 0x04),

	SCU_VARIANT("aspeed,ast2700-scu-ic2",	0, GENMASK(3, 0),	4, 0x04, 0x00),

	SCU_VARIANT("aspeed,ast2700-scu-ic3",	0, GENMASK(1, 0),	2, 0x04, 0x00),

};



struct aspeed_scu_ic {

	unsigned long		irq_enable;

	unsigned long		irq_shift;

	unsigned int		num_irqs;

	unsigned int reg;

	struct regmap *scu;

	void __iomem		*base;

	struct irq_domain	*irq_domain;

	unsigned long		ier;

	unsigned long		isr;

};



static void aspeed_scu_ic_irq_handler(struct irq_desc *desc)

static inline bool scu_has_split_isr(struct aspeed_scu_ic *scu)

{

	return scu->ier != scu->isr;

}



static void aspeed_scu_ic_irq_handler_combined(struct irq_desc *desc)

{

	unsigned int sts;

	unsigned long bit;

	unsigned long enabled;

	unsigned long max;

	unsigned long status;

	struct aspeed_scu_ic *scu_ic = irq_desc_get_handler_data(desc);

	struct irq_chip *chip = irq_desc_get_chip(desc);

	unsigned int mask = scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT;

	unsigned long bit, enabled, max, status;

	unsigned int sts, mask;



	chained_irq_enter(chip, desc);



	mask = scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT;

	/*

	 * The SCU IC has just one register to control its operation and read

	 * status. The interrupt enable bits occupy the lower 16 bits of the
@@ -66,7 +83,7 @@ static void aspeed_scu_ic_irq_handler(struct irq_desc *desc) 
	 * shifting the status down to get the mapping and then back up to

	 * clear the bit.

	 */

	regmap_read(scu_ic->scu, scu_ic->reg, &sts);

	sts = readl(scu_ic->base);

	enabled = sts & scu_ic->irq_enable;

	status = (sts >> ASPEED_SCU_IC_STATUS_SHIFT) & enabled;
@@ -74,43 +91,83 @@ static void aspeed_scu_ic_irq_handler(struct irq_desc *desc) 
	max = scu_ic->num_irqs + bit;



	for_each_set_bit_from(bit, &status, max) {

		generic_handle_domain_irq(scu_ic->irq_domain,

					  bit - scu_ic->irq_shift);

		generic_handle_domain_irq(scu_ic->irq_domain, bit - scu_ic->irq_shift);

		writel((readl(scu_ic->base) & ~mask) | BIT(bit + ASPEED_SCU_IC_STATUS_SHIFT),

		       scu_ic->base);

	}



	chained_irq_exit(chip, desc);

}



static void aspeed_scu_ic_irq_handler_split(struct irq_desc *desc)

{

	struct aspeed_scu_ic *scu_ic = irq_desc_get_handler_data(desc);

	struct irq_chip *chip = irq_desc_get_chip(desc);

	unsigned long bit, enabled, max, status;

	unsigned int sts, mask;



	chained_irq_enter(chip, desc);



	mask = scu_ic->irq_enable;

	sts = readl(scu_ic->base + scu_ic->isr);

	enabled = sts & scu_ic->irq_enable;

	sts = readl(scu_ic->base + scu_ic->isr);

	status = sts & enabled;



		regmap_write_bits(scu_ic->scu, scu_ic->reg, mask,

				  BIT(bit + ASPEED_SCU_IC_STATUS_SHIFT));

	bit = scu_ic->irq_shift;

	max = scu_ic->num_irqs + bit;



	for_each_set_bit_from(bit, &status, max) {

		generic_handle_domain_irq(scu_ic->irq_domain, bit - scu_ic->irq_shift);

		/* Clear interrupt */

		writel(BIT(bit), scu_ic->base + scu_ic->isr);

	}



	chained_irq_exit(chip, desc);

}



static void aspeed_scu_ic_irq_mask(struct irq_data *data)

static void aspeed_scu_ic_irq_mask_combined(struct irq_data *data)

{

	struct aspeed_scu_ic *scu_ic = irq_data_get_irq_chip_data(data);

	unsigned int mask = BIT(data->hwirq + scu_ic->irq_shift) |

		(scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT);

	unsigned int bit = BIT(data->hwirq + scu_ic->irq_shift);

	unsigned int mask = bit | (scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT);



	/*

	 * Status bits are cleared by writing 1. In order to prevent the mask

	 * operation from clearing the status bits, they should be under the

	 * mask and written with 0.

	 */

	regmap_update_bits(scu_ic->scu, scu_ic->reg, mask, 0);

	writel(readl(scu_ic->base) & ~mask, scu_ic->base);

}



static void aspeed_scu_ic_irq_unmask(struct irq_data *data)

static void aspeed_scu_ic_irq_unmask_combined(struct irq_data *data)

{

	struct aspeed_scu_ic *scu_ic = irq_data_get_irq_chip_data(data);

	unsigned int bit = BIT(data->hwirq + scu_ic->irq_shift);

	unsigned int mask = bit |

		(scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT);

	unsigned int mask = bit | (scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT);



	/*

	 * Status bits are cleared by writing 1. In order to prevent the unmask

	 * operation from clearing the status bits, they should be under the

	 * mask and written with 0.

	 */

	regmap_update_bits(scu_ic->scu, scu_ic->reg, mask, bit);

	writel((readl(scu_ic->base) & ~mask) | bit, scu_ic->base);

}



static void aspeed_scu_ic_irq_mask_split(struct irq_data *data)

{

	struct aspeed_scu_ic *scu_ic = irq_data_get_irq_chip_data(data);

	unsigned int mask = BIT(data->hwirq + scu_ic->irq_shift);



	writel(readl(scu_ic->base) & ~mask, scu_ic->base + scu_ic->ier);

}



static void aspeed_scu_ic_irq_unmask_split(struct irq_data *data)

{

	struct aspeed_scu_ic *scu_ic = irq_data_get_irq_chip_data(data);

	unsigned int bit = BIT(data->hwirq + scu_ic->irq_shift);



	writel(readl(scu_ic->base) | bit, scu_ic->base + scu_ic->ier);

}



static int aspeed_scu_ic_irq_set_affinity(struct irq_data *data,
@@ -120,17 +177,29 @@ static int aspeed_scu_ic_irq_set_affinity(struct irq_data *data, 
	return -EINVAL;

}



static struct irq_chip aspeed_scu_ic_chip = {

static struct irq_chip aspeed_scu_ic_chip_combined = {

	.name			= "aspeed-scu-ic",

	.irq_mask		= aspeed_scu_ic_irq_mask,

	.irq_unmask		= aspeed_scu_ic_irq_unmask,

	.irq_mask		= aspeed_scu_ic_irq_mask_combined,

	.irq_unmask		= aspeed_scu_ic_irq_unmask_combined,

	.irq_set_affinity       = aspeed_scu_ic_irq_set_affinity,

};



static struct irq_chip aspeed_scu_ic_chip_split = {

	.name			= "ast2700-scu-ic",

	.irq_mask		= aspeed_scu_ic_irq_mask_split,

	.irq_unmask		= aspeed_scu_ic_irq_unmask_split,

	.irq_set_affinity       = aspeed_scu_ic_irq_set_affinity,

};



static int aspeed_scu_ic_map(struct irq_domain *domain, unsigned int irq,

			     irq_hw_number_t hwirq)

{

	irq_set_chip_and_handler(irq, &aspeed_scu_ic_chip, handle_level_irq);

	struct aspeed_scu_ic *scu_ic = domain->host_data;



	if (scu_has_split_isr(scu_ic))

		irq_set_chip_and_handler(irq, &aspeed_scu_ic_chip_split, handle_level_irq);

	else

		irq_set_chip_and_handler(irq, &aspeed_scu_ic_chip_combined, handle_level_irq);

	irq_set_chip_data(irq, domain->host_data);



	return 0;
@@ -143,21 +212,21 @@ static const struct irq_domain_ops aspeed_scu_ic_domain_ops = { 
static int aspeed_scu_ic_of_init_common(struct aspeed_scu_ic *scu_ic,

					struct device_node *node)

{

	int irq;

	int rc = 0;

	int irq, rc = 0;



	if (!node->parent) {

		rc = -ENODEV;

	scu_ic->base = of_iomap(node, 0);

	if (IS_ERR(scu_ic->base)) {

		rc = PTR_ERR(scu_ic->base);

		goto err;

	}



	scu_ic->scu = syscon_node_to_regmap(node->parent);

	if (IS_ERR(scu_ic->scu)) {

		rc = PTR_ERR(scu_ic->scu);

		goto err;

	if (scu_has_split_isr(scu_ic)) {

		writel(AST2700_SCU_IC_STATUS, scu_ic->base + scu_ic->isr);

		writel(0, scu_ic->base + scu_ic->ier);

	} else {

		writel(ASPEED_SCU_IC_STATUS, scu_ic->base);

		writel(0, scu_ic->base);

	}

	regmap_write_bits(scu_ic->scu, scu_ic->reg, ASPEED_SCU_IC_STATUS, ASPEED_SCU_IC_STATUS);

	regmap_write_bits(scu_ic->scu, scu_ic->reg, ASPEED_SCU_IC_ENABLE, 0);



	irq = irq_of_parse_and_map(node, 0);

	if (!irq) {
@@ -166,75 +235,60 @@ static int aspeed_scu_ic_of_init_common(struct aspeed_scu_ic *scu_ic, 
	}



	scu_ic->irq_domain = irq_domain_create_linear(of_fwnode_handle(node), scu_ic->num_irqs,

						   &aspeed_scu_ic_domain_ops,

						   scu_ic);

						      &aspeed_scu_ic_domain_ops, scu_ic);

	if (!scu_ic->irq_domain) {

		rc = -ENOMEM;

		goto err;

	}



	irq_set_chained_handler_and_data(irq, aspeed_scu_ic_irq_handler,

	irq_set_chained_handler_and_data(irq, scu_has_split_isr(scu_ic) ?

					 aspeed_scu_ic_irq_handler_split :

					 aspeed_scu_ic_irq_handler_combined,

					 scu_ic);



	return 0;



err:

	kfree(scu_ic);



	return rc;

}



static int __init aspeed_scu_ic_of_init(struct device_node *node,

					struct device_node *parent)

static const struct aspeed_scu_ic_variant *aspeed_scu_ic_find_variant(struct device_node *np)

{

	struct aspeed_scu_ic *scu_ic = kzalloc(sizeof(*scu_ic), GFP_KERNEL);



	if (!scu_ic)

		return -ENOMEM;



	scu_ic->irq_enable = ASPEED_SCU_IC_ENABLE;

	scu_ic->irq_shift = ASPEED_SCU_IC_SHIFT;

	scu_ic->num_irqs = ASPEED_SCU_IC_NUM_IRQS;

	scu_ic->reg = ASPEED_SCU_IC_REG;



	return aspeed_scu_ic_of_init_common(scu_ic, node);

	for (int i = 0; i < ARRAY_SIZE(scu_ic_variants); i++) {

		if (of_device_is_compatible(np, scu_ic_variants[i].compatible))

			return &scu_ic_variants[i];

	}



static int __init aspeed_ast2600_scu_ic0_of_init(struct device_node *node,

						 struct device_node *parent)

{

	struct aspeed_scu_ic *scu_ic = kzalloc(sizeof(*scu_ic), GFP_KERNEL);



	if (!scu_ic)

		return -ENOMEM;



	scu_ic->irq_enable = ASPEED_AST2600_SCU_IC0_ENABLE;

	scu_ic->irq_shift = ASPEED_AST2600_SCU_IC0_SHIFT;

	scu_ic->num_irqs = ASPEED_AST2600_SCU_IC0_NUM_IRQS;

	scu_ic->reg = ASPEED_AST2600_SCU_IC0_REG;



	return aspeed_scu_ic_of_init_common(scu_ic, node);

	return NULL;

}



static int __init aspeed_ast2600_scu_ic1_of_init(struct device_node *node,

						 struct device_node *parent)

static int __init aspeed_scu_ic_of_init(struct device_node *node, struct device_node *parent)

{

	struct aspeed_scu_ic *scu_ic = kzalloc(sizeof(*scu_ic), GFP_KERNEL);

	const struct aspeed_scu_ic_variant *variant;

	struct aspeed_scu_ic *scu_ic;



	variant = aspeed_scu_ic_find_variant(node);

	if (!variant)

		return -ENODEV;



	scu_ic = kzalloc(sizeof(*scu_ic), GFP_KERNEL);

	if (!scu_ic)

		return -ENOMEM;



	scu_ic->irq_enable = ASPEED_AST2600_SCU_IC1_ENABLE;

	scu_ic->irq_shift = ASPEED_AST2600_SCU_IC1_SHIFT;

	scu_ic->num_irqs = ASPEED_AST2600_SCU_IC1_NUM_IRQS;

	scu_ic->reg = ASPEED_AST2600_SCU_IC1_REG;

	scu_ic->irq_enable	= variant->irq_enable;

	scu_ic->irq_shift	= variant->irq_shift;

	scu_ic->num_irqs	= variant->num_irqs;

	scu_ic->ier		= variant->ier;

	scu_ic->isr		= variant->isr;



	return aspeed_scu_ic_of_init_common(scu_ic, node);

}



IRQCHIP_DECLARE(ast2400_scu_ic, "aspeed,ast2400-scu-ic", aspeed_scu_ic_of_init);

IRQCHIP_DECLARE(ast2500_scu_ic, "aspeed,ast2500-scu-ic", aspeed_scu_ic_of_init);

IRQCHIP_DECLARE(ast2600_scu_ic0, "aspeed,ast2600-scu-ic0",

		aspeed_ast2600_scu_ic0_of_init);

IRQCHIP_DECLARE(ast2600_scu_ic1, "aspeed,ast2600-scu-ic1",

		aspeed_ast2600_scu_ic1_of_init);
 
IRQCHIP_DECLARE(ast2600_scu_ic0, "aspeed,ast2600-scu-ic0", aspeed_scu_ic_of_init);

IRQCHIP_DECLARE(ast2600_scu_ic1, "aspeed,ast2600-scu-ic1", aspeed_scu_ic_of_init);

IRQCHIP_DECLARE(ast2700_scu_ic0, "aspeed,ast2700-scu-ic0", aspeed_scu_ic_of_init);

IRQCHIP_DECLARE(ast2700_scu_ic1, "aspeed,ast2700-scu-ic1", aspeed_scu_ic_of_init);

IRQCHIP_DECLARE(ast2700_scu_ic2, "aspeed,ast2700-scu-ic2", aspeed_scu_ic_of_init);

IRQCHIP_DECLARE(ast2700_scu_ic3, "aspeed,ast2700-scu-ic3", aspeed_scu_ic_of_init);