Unverified Commit 0420af54 authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

Merge patch series "membarrier: riscv: Core serializing command" 

RISC-V was lacking a membarrier implementation for the store/fetch
ordering, which is a bit tricky because of the deferred icache flushing
we use in RISC-V.

* b4-shazam-merge:
  membarrier: riscv: Provide core serializing command
  locking: Introduce prepare_sync_core_cmd()
  membarrier: Create Documentation/scheduler/membarrier.rst
  membarrier: riscv: Add full memory barrier in switch_mm()

Link: https://lore.kernel.org/r/20240131144936.29190-1-parri.andrea@gmail.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parents cb4ede92 cd9b2901

Documentation/features/sched/membarrier-sync-core/arch-support.txt

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@@ -10,6 +10,22 @@ 
# Rely on implicit context synchronization as a result of exception return

# when returning from IPI handler, and when returning to user-space.

#

# * riscv

#

# riscv uses xRET as return from interrupt and to return to user-space.

#

# Given that xRET is not core serializing, we rely on FENCE.I for providing

# core serialization:

#

#  - by calling sync_core_before_usermode() on return from interrupt (cf.

#    ipi_sync_core()),

#

#  - via switch_mm() and sync_core_before_usermode() (respectively, for

#    uthread->uthread and kthread->uthread transitions) before returning

#    to user-space.

#

#  The serialization in switch_mm() is activated by prepare_sync_core_cmd().

#

# * x86

#

# x86-32 uses IRET as return from interrupt, which takes care of the IPI.
@@ -43,7 +59,7 @@ 
    |    openrisc: | TODO |

    |      parisc: | TODO |

    |     powerpc: |  ok  |

    |       riscv: | TODO |

    |       riscv: |  ok  |

    |        s390: |  ok  |

    |          sh: | TODO |

    |       sparc: | TODO |

Documentation/scheduler/index.rst

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@@ -7,6 +7,7 @@ Scheduler 




    completion

    membarrier

    sched-arch

    sched-bwc

    sched-deadline

Documentation/scheduler/membarrier.rst

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.. SPDX-License-Identifier: GPL-2.0



========================

membarrier() System Call

========================



MEMBARRIER_CMD_{PRIVATE,GLOBAL}_EXPEDITED - Architecture requirements

=====================================================================



Memory barriers before updating rq->curr

----------------------------------------



The commands MEMBARRIER_CMD_PRIVATE_EXPEDITED and MEMBARRIER_CMD_GLOBAL_EXPEDITED

require each architecture to have a full memory barrier after coming from

user-space, before updating rq->curr.  This barrier is implied by the sequence

rq_lock(); smp_mb__after_spinlock() in __schedule().  The barrier matches a full

barrier in the proximity of the membarrier system call exit, cf.

membarrier_{private,global}_expedited().



Memory barriers after updating rq->curr

---------------------------------------



The commands MEMBARRIER_CMD_PRIVATE_EXPEDITED and MEMBARRIER_CMD_GLOBAL_EXPEDITED

require each architecture to have a full memory barrier after updating rq->curr,

before returning to user-space.  The schemes providing this barrier on the various

architectures are as follows.



 - alpha, arc, arm, hexagon, mips rely on the full barrier implied by

   spin_unlock() in finish_lock_switch().



 - arm64 relies on the full barrier implied by switch_to().



 - powerpc, riscv, s390, sparc, x86 rely on the full barrier implied by

   switch_mm(), if mm is not NULL; they rely on the full barrier implied

   by mmdrop(), otherwise.  On powerpc and riscv, switch_mm() relies on

   membarrier_arch_switch_mm().



The barrier matches a full barrier in the proximity of the membarrier system call

entry, cf. membarrier_{private,global}_expedited().

MAINTAINERS

+3 −1
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@@ -14039,7 +14039,9 @@ M: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> 
M:	"Paul E. McKenney" <paulmck@kernel.org>

L:	linux-kernel@vger.kernel.org

S:	Supported

F:	arch/powerpc/include/asm/membarrier.h

F:	Documentation/scheduler/membarrier.rst

F:	arch/*/include/asm/membarrier.h

F:	arch/*/include/asm/sync_core.h

F:	include/uapi/linux/membarrier.h

F:	kernel/sched/membarrier.c
































arch/riscv/Kconfig



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−0






























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@@ -27,14 +27,18 @@ config RISCV







	select ARCH_HAS_GCOV_PROFILE_ALL









	select ARCH_HAS_GIGANTIC_PAGE









	select ARCH_HAS_KCOV









	select ARCH_HAS_MEMBARRIER_CALLBACKS









	select ARCH_HAS_MEMBARRIER_SYNC_CORE









	select ARCH_HAS_MMIOWB









	select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE









	select ARCH_HAS_PMEM_API









	select ARCH_HAS_PREPARE_SYNC_CORE_CMD









	select ARCH_HAS_PTE_SPECIAL









	select ARCH_HAS_SET_DIRECT_MAP if MMU









	select ARCH_HAS_SET_MEMORY if MMU









	select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL









	select ARCH_HAS_STRICT_MODULE_RWX if MMU && !XIP_KERNEL









	select ARCH_HAS_SYNC_CORE_BEFORE_USERMODE









	select ARCH_HAS_SYSCALL_WRAPPER









	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST









	select ARCH_HAS_UBSAN_SANITIZE_ALL